m58wr032qt Numonyx, m58wr032qt Datasheet
m58wr032qt
Related parts for m58wr032qt
m58wr032qt Summary of contents
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... Mbit and 32 Mbit (x16, Multiple Bank, Burst) 1.8V supply Flash memories ■ Electronic signature – Manufacturer Code: 20h – Device Codes: M58WR016QT (Top): 8812h. M58WR016QB (Bottom): 8813h M58WR032QT (Top): 8814h M58WR032QB (Bottom): 8815h ■ ECOPACK® package available Rev 2 FBGA VFBGA56 (ZB) 7 1/110 www ...
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... DDQ 2.13 V Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PP 2.14 V Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SS 2.15 V Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SSQ 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 Command interface - standard commands . . . . . . . . . . . . . . . . . . . . . 20 5.1 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 5.3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.7 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.8 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.9 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.10 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.11 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.12 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.13 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 ...
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... Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 52 12 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 54 13 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Block Protection Status Bit (SR1 Bank Write/Multiple Word Program Status Bit (SR0 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 16 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 C.1 Enhanced Factory Program pseudo code 102 C.2 Quadruple Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . 104 Appendix D Command interface state tables 105 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ...
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... Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 28. Daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 29. Top boot block addresses, M58WR016QT Table 30. Bottom boot block addresses, M58WR016QB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 31. Top boot block addresses, M58WR032QT Table 32. Bottom boot block addresses, M58WR032QB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 33. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 34. CFI Query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 35. ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB List of figures Figure 1. Logic Diagram Figure 2. VFBGA Connections (Top view through package Figure 3. M58WR016QT/B memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. M58WR032QT/B memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 6. X-Latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 7. Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 8. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 9 ...
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... KWords and 7 main blocks of 32 KWords. ● M58WR032QT/B has an array of 71 blocks, and is divided into 4 Mbit banks. There are 7 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords. ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V program or erase. All blocks are locked at Power- Up. The device includes a Protection Register to increase the protection of a system’s design. The Protection Register is divided into two segments bit segment containing a unique device number written by Numonyx, and a 128 bit segment One-Time-Programmable (OTP) by the user ...
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... Summary description Figure 1. Logic Diagram 1. Amax is equal to A19 for the M58WR016QT/B and to A20 for the M58WR032QT/B. Table 1. Signal names (1) A0-Amax DQ0-DQ15 WAIT DDQ SSQ NC 1. Amax is equal to A19 for the M58WR016QT/B and to A20 for the M58WR032QT/B. ...
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... VFBGA Connections (Top view through package A11 B A12 C A13 D A15 E V DDQ DQ7 1. Ball B3 is A20 in the M58WR032QT/B and it is Not Connected internally (NC) in the M58WR016QT/B. Table 2. M58WR016QT/B Bank architecture Number Parameter Bank Bank 1 Bank 2 Bank ...
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... Bank 1 B8000h BFFFFh C0000h C7FFFh F0000h Parameter F7FFFh Bank F8000h F8FFFh FF000h FFFFFh 12/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Bank Size Parameter Blocks 4 Mbits 8 blocks of 4 KWords 4 Mbits 4 Mbits 4 Mbits 4 Mbits 4 Mbits Address lines A0-A19 32 KWord 8 Main Blocks 32 KWord Parameter ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Figure 4. M58WR032QT/B memory map M58WR032QT - Top Boot Block 000000h 007FFFh Bank 7 038000h 03FFFFh 100000h 107FFFh Bank 3 138000h 13FFFFh 140000h 147FFFh Bank 2 178000h 17FFFFh 180000h 187FFFh Bank 1 1B8000h 1BFFFFh 1C0000h 1C7FFFh 1F0000h Parameter 1F7FFFh Bank 1F8000h 1F8FFFh 1FF000h ...
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... Address Inputs (A0-Amax) Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 2.7 Reset (RP) The Reset input provides a hardware reset of the memory. When Reset memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I for the value of I DD2. Register is reset. When Reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs ...
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... Each device in a system should have V capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See track widths should be sufficient to carry the required V 16/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ) V is seen as a control input. In this case a voltage lower than DDQ PP 19 and 20, DC Characteristics for the relevant values) ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 3 Bus operations There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations ...
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... Standby Reset Don't care. 2. WAIT signal polarity is configured using the Set Configuration Register command can be tied Depends on G. 18/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB . The power consumption is reduced to the IL during a Program or Erase, this operation is aborted and the memory SS (1) E ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 4 Command interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation ...
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... Read cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. 20/110 M58WR016QT, M58WR016QB, M58WR032QT, commands, in conjunction with the following text . Either must be toggled to update the latched data. See IH Table 7) ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com- 5.4 Read CFI Query command The Read CFI Query command is used to read data from the Common Flash Interface (CFI). The Read CFI Query Command consists of one Bus Write cycle address within one of the banks. Once the command is issued subsequent Bus Read operations in the same bank read from the Common Flash Interface ...
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... Programming aborts if Reset goes to V program operation is aborted, the memory location must be reprogrammed. See Appendix C, the Program command. 22/110 M58WR016QT, M58WR016QB, M58WR032QT, Figure 24: Block Erase flowchart and pseudo . As data integrity cannot be guaranteed when the IL Figure 20: Program flowchart and pseudo . As data integrity cannot IL ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com- 5.8 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Program/Erase command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to ‘ ...
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... Read operations output the memory array content after the Set Configuration Register command is issued. The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1 on A1, etc.; the other address bits are ignored. 24/110 M58WR016QT, M58WR016QB, M58WR032QT, Map). Attempting to program a previously protected Appendix code, for a flowchart for using the C, ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com- 5.12 Block Lock command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. ...
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... ESD=Electronic Signature Data, QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data, CRD=Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in 3. Any address within the bank can be used. 26/110 M58WR016QT, M58WR016QB, M58WR032QT, (1) Bus Operations 1st Cycle Op. Add ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com- Table 7. Electronic signature codes Manufacturer Code Device Code Block Protection Reserved Configuration Register Protection Register Lock Protection Register Configuration Register. Figure 5. Protection Register Memory Map Code Bank Address + 00 Top Bank Address + 01 Bottom ...
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... Dual Operations are not supported during Bank Erase operations and the command cannot be suspended. Typical Erase times are given in 28/110 M58WR016QT, M58WR016QB, M58WR032QT, commands, in conjunction with the following text descriptions. (except for Bank Erase comand), PPH must be 25°C ± 5°C, ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 6.2 Double Word Program command The Double Word Program command improves the programming throughput by writing a page of two adjacent words in parallel. The two words must differ only for the address A0. If the block is protected, the Double Word Program operation will abort, the data in the block will not be changed and the Status Register will output the error ...
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... Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Refer to Factory Program 30/110 M58WR016QT, M58WR016QB, M58WR032QT data integrity cannot be guaranteed when the IL cycles. Figure 22: Quadruple Word Program flowchart and pseudo Table 15 ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 6.4.1 Setup Phase The Enhanced Factory Program command requires two Bus Write operations to initiate the command. ● The first bus cycle sets up the Enhanced Factory Program command. ● The second bus cycle confirms the command. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready. After the confirm command is issued, read operations output the Status Register data ...
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... Exit Phase. Unlike the Enhanced Factory Program it is not necessary to resubmit the data for the Verify Phase. The Load Phase and the Program and Verify Phase can be repeated to program any number of pages within the block. 32/110 M58WR016QT, M58WR016QB, M58WR032QT, ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 6.5.1 Setup Phase The Quadruple Enhanced Factory Program command requires one Bus Write operation to initiate the load phase. After the setup command is issued, read operations output the Status Register data. The Read Status Register command must not be issued as it will be interpreted as data to program ...
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... Address can remain Starting Address WA1 or be incremented. 9. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent Words in each Page can be written to any address. 34/110 M58WR016QT, M58WR016QB, M58WR032QT, (1) Bus Write Operations 1st ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 7 Status Register The Status Register provides information on the current or previous Program or Erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable ...
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... Lockout Voltage operations cannot be performed. Once set High, the V command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 36/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB = PPH = V ( different from V ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 7.0.6 Program Suspend Status Bit (SR2) The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command ...
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... Program Suspend SR2 Status Block Protection SR1 Status Bank Write Status SR0 Multiple Word Program Status (Enhanced Factory Program mode) 1. Logic level '1' is High, '0' is Low. 38/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Logic Type (1) Level '1' Ready Status '0' Busy '1' Erase Suspended Status '0' Erase In progress or Completed ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 8 Configuration Register The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power- Up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in type, burst X latency and the Read operation ...
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... The burst reads can be confined inside the Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When 40/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB QVK_CPU is the data setup time required by the system CPU QVK_CPU example ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap. 8.9 Burst length Bits (CR2-CR0) The Burst Length bits set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle ...
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... CR8 Wait Configuration CR7 Burst Type CR6 Valid Clock Edge CR5-CR4 Reserved CR3 Wrap Burst CR2-CR0 Burst Length 42/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Description Value 0 Synchronous Read 1 Asynchronous Read (Default at power-on) 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 11. Burst type definition 4 Words Start Add Sequential Interleaved Sequential Interleaved 0 0-1-2-3 0-1-2-3 1 1-2-3-0 1-0-3-2 2 2-3-0-1 2-3-0-1 3 3-0-1-2 3-2-1-0 ... 7 7-4-5-6 7-6-5-4 ... Words Sequential 0-1-2-3-4-5- 0-1-2-3-4-5- 0-1-2-3-4-5-6-7-8-9- 6-7 6-7 10-11-12-13-14-15 1-2-3-4-5-6-7-8-9- 1-2-3-4-5-6- 1-0-3-2-5-4- 10-11-12-13-14-15- 7-0 7-6 2-3-4-5-6-7- 2-3-0-1-6-7- 2-3-4-5-6-7-8-9-10- 0-1 4-5 11-12-13-14-15-0-1 3-4-5-6-7-8-9-10- 3-4-5-6-7-0- 3-2-1-0-7-6- 11-12-13-14-15-0- 1-2 5-4 7-0-1-2-3-4- 7-6-5-4-3-2- 7-8-9-10-11-12-13- 5-6 1-0 14-15-0-1-2-3-4-5-6 Configuration Register 16 Words Continuous Burst Interleaved 0-1-2-3-4-5-6- 7-8-9-10-11- 0-1-2-3-4-5-6... 12-13-14-15 1-0-3-2-5-4-7- 1-2-3-4-5-6-7- 6-9-8-11-10- ...15-WAIT-16- 0 13-12-15-14 17-18... 2-3-0-1-6-7-4- 2-3-4-5-6-7...15- 5-10-11-8-9- WAIT-WAIT-16- 14-15-12-13 17-18... 3-2-1-0-7-6-5- 3-4-5-6-7...15- 4-11-10-9-8- WAIT-WAIT- 1-2 15-14-13-12 WAIT-16-17-18... 7-8-9-10-11-12- 7-6-5-4-3-2-1- 13-14-15-WAIT- 0-15-14-13- WAIT-WAIT-16- 12-11-10-9-8 12-13-14-15-16- 17-18... 13-14-15-WAIT- 16-17-18... 14-15-WAIT- WAIT-16-17- 15-WAIT-WAIT- WAIT-16-17-18... ...
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... X-Latency and data output configuration example 1st cycle Amax-A0 VALID ADDRESS 44/110 tDELAY tAVK_CPU DQ15-DQ0 Notes: 1. Settings shown: X-latency = 4, Data Output held for one clock cycle. 2. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B. M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 8 Words 16 Words Sequential 0-1-2-3-4-5-6-7-8-9- 6-7 10-11-12-13-14-15 1-2-3-4-5-6-7-8-9- 10-11-12-13-14-15- 7-8 WAIT-16 ...
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... Wait configuration example (1) Amax-A0 VALID ADDRESS DQ15-DQ0 WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1' Note: Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B. Configuration Register VALID DATA VALID DATA NOT VALID VALID DATA AI10175 45/110 ...
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... In Asynchronous Read mode, the WAIT signal is always asserted. See Table 21: Asynchronous Read AC Access Read AC details. 46/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB characteristics, waveforms, and Figure 11: Asynchronous Page Read AC waveforms 12 and 13). , Random access ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 9.2 Synchronous Burst Read mode In Synchronous Burst Read mode the data is output in bursts synchronized with the clock possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used ...
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... Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is always asserted. See Table 22: Synchronous Read AC characteristics Read AC waveforms, for details. 48/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB and G goes high waveforms, for details. and Figure 14: Synchronous Burst ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 10 Dual operations and Multiple Bank architecture The Multiple Bank Architecture of the M58WRxxxQT/B provides flexibility for software developers by allowing code and data to be split with 4Mbit granularity. The Dual Operations feature simplifies the software management of the device and allows code to be executed from one bank while another bank is being programmed or erased ...
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... Yes Suspended 1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed. 2. Not allowed in the Block or Word that is being erased or programmed. 50/110 M58WR016QT, M58WR016QB, M58WR032QT, Commands allowed in same bank Read Read Read Status CFI ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 11 Block locking The M58WRxxxQT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. ● Lock/Unlock - this first level allows software-only control of block locking. ● ...
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... Locking operations cannot be performed during a program suspend. Refer to Appendix Appendix D: Command interface state commands are valid during erase suspend. 52/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ) the Lock-Down function is disabled (1,1,x) and Locked-Down IH tables, for detailed information on which ), the blocks in IL ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 14. Lock status Current Protection Status (WP, DQ1, DQ0) Current Program/Erase State Allowed 1,0,0 (2) 1,0,1 1,1,0 1,1,1 0,0,0 (2) 0,0,1 0,1,1 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read in the Read Electronic Signature command with ...
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... Table 15. Program/Erase times and endurance cycles Parameter Erase (3) Program Suspend Latency Program/Erase Cycles (per Block) 54/110 M58WR016QT, M58WR016QB, M58WR032QT, Condition (2) Parameter Block (4 KWord) Preprogrammed Main Block (32 KWord) Not Preprogrammed Preprogrammed Bank (4Mbit) Not Preprogrammed Word Parameter Block (4 KWord) ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Program and erase times and endur- Table 15. Program/Erase times and endurance cycles Parameter Erase (3) Program Program/Erase Cycles (per Block –40 to 85° The difference between Preprogrammed and not preprogrammed is not significant (‹30ms). 3. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). 4. Measurements performed at 25° ...
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... Input or Output Voltage IO V Supply Voltage DD V Input/Output Supply Voltage DDQ V Program Voltage PP I Output Short Circuit Current O t Time for V VPPH 56/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Parameter PPH Value Unit Min Max –40 85 °C –40 125 °C –65 155 °C – ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 14 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 17: Operating and AC measurement operating conditions in their circuit match the operating conditions when relying on the quoted parameters ...
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... DC and AC parameters Figure 9. AC measurement load circuit Table 18. Capacitance Symbol C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested. 58/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB V DDQ V DD DEVICE UNDER TEST 0.1µF 0.1µ includes JIG capacitance (1) Parameter Test Condition ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 19. DC characteristics - currents Symbol I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=6MHz) Supply Current Synchronous Read (f=54MHz) I DD1 Supply Current Synchronous Read (f=66MHz) I Supply Current (Reset) DD2 I Supply Current (Standby) DD3 Supply Current (Automatic ...
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... PP V PPH Factory Program or Erase V PPLK Lockout V V Lock Voltage LKO DD RP pin Extended High V RPH Voltage 60/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Test Condition V DDQ I = 100µ –100µ DDQ Program, Erase Program, Erase Min Typ Max Unit –0.5 0.4 – ...
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... A0-Amax tAVLH L tLLLH tELLH E G Hi-Z WAIT Hi-Z DQ0-DQ15 Valid Address Latch Notes: 1. Write Enable High, WAIT is active Low. 2. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B. VALID tAVAV tLHAX tLLQV tLHGL tELQV tELQX tGLQV tGLQX tELTV tAVQV Outputs Enabled DC and AC parameters ...
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... DC and AC parameters Figure 11. Asynchronous Page Read AC waveforms 62/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 21. Asynchronous Read AC characteristics Symbol t AVAV t AVQV t t AVQV1 (1) t AXQX t ELTV (2) t ELQV (1) t ELQX t EHTZ (1) t EHQX (1) t EHQZ (2) t GLQV (1) t GLQX (1) t GHQX (1) t GHQZ t t AVLH AVADVH t t ELLH ELADVH t t LHAX ...
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... DC and AC parameters Figure 12. Synchronous Burst Read AC waveforms 64/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Figure 13. Single Synchronous Read AC waveforms DC and AC parameters 65/110 ...
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... DC and AC parameters Figure 14. Synchronous Burst Read Suspend AC waveforms 66/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Figure 15. Clock input AC waveform Table 22. Synchronous Read AC characteristics Symbol t t AVKH AVCLKH t t ELKH ELCLKH t ELTV t EHEL t EHTZ t t KHAX CLKHAX t KHQV t CLKHQV t KHTV t KHQX t CLKHQX t KHTX t t LLKH ADVLCLKH t KHKH t KHKL t KLKH Sampled only, not 100% tested. ...
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... DC and AC parameters Figure 16. Write AC waveforms, Write Enable controlled 68/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 23. Write AC characteristics, Write Enable controlled Symbol Alt t t AVAV WC t AVLH (2) t AVWH t t DVWH DS t ELLH t t ELWL CS t ELQV t ELKV t GHWL t LHAX t LLLH (2) t WHAV ( WHAX WHDX WHEH CH (3) t WHEL t WHGL ...
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... DC and AC parameters Figure 17. Write AC waveforms, Chip Enable controlled 70/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 24. Write AC characteristics, Chip Enable controlled Symbol Alt t t AVAV WC t AVEH t AVLH t t DVEH EHAX EHDX EHEL CPH t EHGL t t EHWH CH t ELKV t t ELEH CP t ELLH t ELQV t GHEL t LHAX t LLLH (2) t WHEL ...
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... VDHPH High 1. The device Reset is possible but not guaranteed Sampled only, not 100% tested important to assert RP in order to allow proper CPU initialization during Power-Up or Reset. 72/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB tPHWL tPHEL tPHGL tPHLL Power-Up Test Condition During Program ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 15 Package mechanical Figure 19. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline Drawing is not to scale. Table 26. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, package mechanical data Symbol Typ 0.660 b 0.350 D 7.700 D1 5.250 ...
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... Package ZB = VFBGA56, 7.7x9mm, 0.75mm pitch Temperature Range 6 = –40 to 85°C Option Blank = Standard Packing T = Tape & Reel Packing E = ECOPACK® Package, Standard Packing F = ECOPACK® Package, Tape & Reel Packing 74/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB M58WR016QT = 1.7V to 2.24V DDQ ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 28. Daisy chain ordering scheme Example: Device Type M58WR016Q Daisy Chain ZB = VFBGA56, 7.7x9mm, 0.75mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = ECOPACK® Package, Standard Packing F = ECOPACK®, Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc ...
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... Block address tables Appendix A Block address tables Table 29. Top boot block addresses, M58WR016QT (1) Bank 76/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB # Size (KWord ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 29. Top boot block addresses, M58WR016QT (continued) 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). ...
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... There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 31. Top boot block addresses, M58WR032QT (1) Bank ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 31. Top boot block addresses, M58WR032QT (continued ...
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... Block address tables Table 31. Top boot block addresses, M58WR032QT (continued) 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 32. Bottom boot block addresses, M58WR032QB (continued ...
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... Bottom boot block addresses, M58WR032QB (continued) 1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank). 82/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Appendix B Common Flash Interface The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory ...
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... A = 0000h Address for Alternate Algorithm extended 1Ah 0000h 84/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Description Manufacturer Code Device Code Reserved reserved Reserved Query Unique ASCII String "QRY" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 35. CFI query system interface information Offset Data 1Bh 0017h 1Ch 0020h 1Dh 00B4h 1Eh 00C6h 1Fh 0004h 20h 0000h 21h 000Ah 22h 0000h 23h 0003h 24h 0000h 25h 0002h 26h 0000h Description V Logic Supply Minimum Program/Erase or Write voltage ...
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... Erase Block Region 1 Information Block size in Region 1 = 0020h * 256 byte M58WR016QT/B Erase Block Region 2 Information Number of identical-size erase block = 001Eh+1 M58WR032QT/B Erase Block Region 2 Information Number of identical-size erase block = 003Eh+1 Erase Block Region 2 Information Block size in Region 2 = 0100h * 256 byte Value ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 37. Primary algorithm-specific extended query table Offset (P)h = 39h 0050h 0052h 0049h (P+3)h = 3Ch 0031h (P+4)h = 3Dh 0033h (P+5)h = 3Eh 00E6h 0003h (P+7)h = 40h 0000h (P+8)h = 41h 0000h (P+9)h = 42h 0001h (P+A)h = 43h 0003h (P+B)h = 44h 0000h (P+C)h = 45h 0018h (P+D)h = 46h 00C0h Data Primary Algorithm extended Query table unique ASCII string “ ...
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... The variable pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, see Table 31 and Table 32 88/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Data Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Protection Field 1: Protection Description Bits 0-7 Lower byte of protection register address ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 41. Bank and erase block region 1 information TOP DEVICES Offset Data 03h (P+1A)h = 53h 07h (P+1B)h = 54h (P+1C)h = 55h (P+1D)h = 56h (P+1E)h = 57h (P+1F)h = 58h (P+20)h = 59h (P+21)h = 5Ah (P+22)h = 5Bh (P+23)h = 5Ch (P+24)h = 5Dh (P+25)h = 5Eh (P+26)h = 5Fh (P+27)h = 60h BOTTOM DEVICES Offset Data (2) (P+1A)h = 53h 01h (3) Number of identical banks within Bank Region 1 ...
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... Bank and erase block region 1 information TOP DEVICES Offset Data 1. The variable pointer which is defined at CFI offset 15h. 2. Applies to the M58WR016QT/B only. 3. Applies to the M58WR032QT/B only. 4. Bank Regions. There are two Bank Regions, see Table 31 and Table 32 90/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 42. Bank and erase block region 2 information TOP DEVICES Offset Data (P+28)h = 61h 01h (P+29)h = 62h 00h (P+2A)h = 63h 11h (P+2B)h = 64h 00h (P+2C)h = 65h 00h (P+2D)h = 66h 02h (P+2E)h = 67h 06h (P+2F)h = 68h 00h (P+30)h = 69h 00h (P+31)h = 6Ah 01h (P+32)h = 6Bh 64h (P+33)h = 6Ch 00h (P+34)h = 6Dh 01h ...
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... The variable pointer which is defined at CFI offset 15h. 2. Applies to the M58WR016QT/B only. 3. Applies to the M58WR032QT/B only. 4. Bank Regions. There are two Bank Regions, see Table 31 and Table 32 92/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB BOTTOM DEVICES ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Appendix C Flowcharts and pseudo codes Figure 20. Program flowchart and pseudo code Start Write 40h or 10h (3) Write Address & Data Read Status Register (3) NO SR7 = 1 YES NO SR3 = 0 YES NO SR4 = 0 YES NO Program to Protected SR1 = 0 YES End 1. Status check of SR1 (Protected Block), SR3 (V operation or after a sequence ...
Page 94
... If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0. 4. Any address within the bank can equally be used. 94/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB double_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (addressToProgram1, 0x35); ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Figure 22. Quadruple Word Program flowchart and pseudo code Start Write 56h Write Address 1 & Data 1 (3, 4) Write Address 2 & Data 2 (3) Write Address 3 & Data 3 (3) Write Address 4 & Data 4 (3) Read Status Register (4) NO SR7 = 1 YES ...
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... Program Continues with Bank in Read Status Register Mode 1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command. 96/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70 read status register to check if ...
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... YES End error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can be used also. 3. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B. erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; writeToFlash (blockToErase, 0xD0 only A12-Amax (3) are significant */ ...
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... Erase Continues with Bank in Read Status Register Mode 1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command. 98/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70 read status register to check if ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Figure 26. Locking operations flowchart and pseudo code Start Write 60h (1) Write 01h, D0h or 2Fh Write 90h (1) Read Block Lock States Locking change confirmed? YES Write FFh (1) End 1. Any address within the bank can equally be used. locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 100/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Figure 28. Enhanced Factory Program flowchart SETUP PHASE NO Check SR4, SR3 and SR1 for program, V and Lock Errors PP Exit PROGRAM PHASE Address Block WA1 1. Address can remain Starting Address WA1 or be incremented. Start Write 30h Address WA1 Write D0h ...
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... Ready for a new data */ } writeToFlash(another_block_address,FFFFh); /* exit program phase */ /* Exit Phase */ /* status register polling */ do{ status_register=readFlash(any_address must be toggled */ } while (status_register.SR7==0); if (status_register.SR4==1) /*program failure error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } } 102/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Figure 29. Quadruple Enhanced Factory Program flowchart SETUP PHASE Start Write 75h Address WA1 FIRST LOAD PHASE Write PD1 Address WA1 Read Status Register NO SR7 = 0? YES Check SR4, SR3 and SR1 for program, PROGRAM AND V and Lock Errors ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB /*Data Load Phase*/ status_register=readFlash(any_address); if (status_register.SR7==1){ if (status_register.SR4==1) /*program error*/ if (status_register.SR3==1) /*VPP invalid error*/ if (status_register.SR1==1) /*program to protect block writeToFlash(addressFlow[i],dataFlow[i,2]); ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Appendix D Command interface state tables Table 43. Command interface states - modify table, next state WP Read Current CI State (3)(4) (2) setup Array (FFh) (10/40h) Program Ready Ready Setup Lock/CR Setup Setup OTP Busy Setup Program Busy Suspend Setup Busy Erase Program ...
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... The two cycle command should be issued to the same bank address the P/E.C. is active, both cycles are ignored. 6. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 106/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command Input Erase Confirm DWP, ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 45. Command interface states - lock table, next state Current CI State Lock/CR (2) Setup (60h) Lock/CR Ready Setup Lock/CR Setup Ready (Lock error) Setup OTP Busy Setup Program Busy Suspend Setup Busy Erase Lock/CR Setup in Suspend Erase Suspend Setup ...
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... If the P/E.C. is active, both cycles are ignored. 3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh. 4. Illegal commands are those not defined in the command set. 108/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command Input Block OTP ...
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... M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 17 Revision history Table 47. Document revision history Date 15-Sep-2004 14-Apr-2006 12-Nov-2007 Revision 0.1 First Issue Document status promoted from Target Specificaton to full Datasheet. Small text changes. Address modified for Clear Status Register command in Table 6: Standard Test condition modified for I characteristics - currents ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 110/110 M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Please Read Carefully: applications. visiting Numonyx's website at http://www.numonyx.com. ...