at17f32 ATMEL Corporation, at17f32 Datasheet - Page 4
at17f32
Manufacturer Part Number
at17f32
Description
Fpga Configuration Flash Memory At17f32
Manufacturer
ATMEL Corporation
Datasheet
1.AT17F32.pdf
(14 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
5. Pin Description
5.1
5.2
5.3
4
DATA
CLK
PAGE_EN
AT17F32
(1)
(1)
(2)
Table 5-1.
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain Low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes:
Name
DATA
CLK
PAGE_EN
PAGESEL0
PAGESEL1
RESET/
CE
GND
CEO
A2
READY
SER_EN
V
CC
1. This pin has an internal 20 K pull-up resistor.
2. This pin has an internal 30 K pull-down resistor.
OE
Pin Description
I/O
I/O
O
O
–
–
I
I
I
I
I
I
I
I
AT17F32
PLCC
44
20
25
19
21
24
27
29
41
44
2
5
1
3393C–CNFG–6/05