at17c010a ATMEL Corporation, at17c010a Datasheet
at17c010a
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at17c010a Summary of contents
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... WP1 pin is used to protect part of the device memory during in-system programming. The AT17A Series can be programmed with industry standard programmers. Pin Configurations 20-Pin PLCC DCLK 4 18 WP1 RESET/ Versions SER_EN NC NC READY NC FPGA Serial Configuration Memories AT17C512A AT17LV512A AT17C010A AT17LV010A Rev. 0974A–04/98 1 ...
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Block Diagram SER_EN OSC CONTROL OSC DCLK Device Configuration The control signals for configuration EEPROMs–nCS, OE, and DCLK–interface directly with the FPGA device control signals. All FPGA devices can control the entire configura- tion process and retrieve data from the ...
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... VCC VCC 1KW 1KW DCLK DCLK DATA0 DATA nCS nSTATUS OE nCE GND AT17C010A AT17C010A Device 1 Device 2 DCLK DATA nCASC nCS OE 3 ...
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Pin Configurations Pin Number (20-Pin PLCC) Pin Name Pin Type 2 DATA Output 4 DCLK 5 WP1 8 RESET/OE 9 nCS 10 GND Ground 12 nCASC Output A2 15 READY Output 18 SER_EN Absolute Maximum Ratings* Operating ...
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Operating Conditions Symbol Description Supply voltage relative to GND Commercial - +70 C Supply voltage relative to GND V Industrial CC - +85 C Supply voltage relative to GND Military - +125 C AT17CXXXA ...
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DC Characteristics Commercial / 5V CC Symbol Description V High-level input voltage IH V Low-level input voltage IL V High-level output voltage ( Low-level output voltage ( High-level output voltage (I OH ...
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AC Characteristics AC Characteristics When Cascading 7 ...
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... MAX Input Clock Frequency Slave Mode MAX T CLK Low Time Master Mode LC T CLK High Time Master Mode HC V Ready Pin Open Collector Voltage RDY AC Characteristics for AT17C010A/512A When Cascading Commercial / Symbol Description (3) T DCLK to Data Float Delay ...
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... MAX Input Clock Frequency Slave Mode MAX T CLK Low Time Master Mode LC T CLK High Time Master Mode HC V Ready Pin Open Collector Voltage RDY AC Characteristics for AT17C010A/512A When Cascading V = 3.3V 10% Commercial / V CC Symbol Description (3) T DCLK to Data Float Delay CDF ...
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... Ordering Information - 5V Devices Memory Size (K) Ordering Code (1) 512K AT17C512A-10JC AT17C512A-10JI (2) 1M Bit AT17C010A-10JC AT17C010A-10JI Ordering Information - 3.3V Devices Memory Size (K) Ordering Code (1) 512K AT17LV512A-10JC AT17LV512A-10JI (2) 1M Bit AT17LV010A-10JC AT17LV010A-10JI Notes: 1. Use 512K density parts to replace Altera EPC1441. 2. Use 1M density parts to replace Altera EPC1 ...
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Packaging Information 20J, 20-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AA 11 ...