ncp5220a ON Semiconductor, ncp5220a Datasheet
ncp5220a
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ncp5220a Summary of contents
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... NCP5220A 3−in−1 PWM Dual Buck and Linear Power Controller The NCP5220A 3−in−1 PWM Dual Buck and Linear Power Controller complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage ...
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... CPM1 RZM2 RZM1 5VDUAL R6 TG_1P5 M3 VMCH L 1 BG_1P5 COUT3 M4 NCP5220A BOOT SS 5VDUAL VTT TG_DDQ FBVTT AGND SW_DDQ NCP5220A BG_DDQ PGND FB1P5 COMP FBDDQ VDDQ PGND Figure 1. Application Diagram http://onsemi.com Zener 5VDUAL M1 VDDQ 2 COUT1 M2 CZ1 CZ2 ...
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... BOOT_ R10 UVLO VREF R11 5VDUAL R12 5VDUAL_ UVLO VREF R13 _5VDLGD SS OSC S0 CSS S3 1805 Phase Shift S0 VTT Regulation Control AGND NCP5220A THERMAL SHUTDOWN TSD S0 CONTROL LOGIC S3 VOCP + ILIM + − VCC VDDQ and V1P5 PGND PWM VCC LOGIC PGND AMP A1 VCC ...
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... This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) "200 V per JEDEC standard: JESD22–A115. 2. Latchup Current Maximum Rating: "150 mA per JEDEC standard: JESD78. NCP5220A Description Symbol ...
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... Minimum Duty Cycle Maximum Duty Cycle Soft−Start Pin Current for DDQ DDQ ERROR AMPLIFIER DC Gain Gain−Bandwidth Product Slew Rate 3. Guaranteed by design, not tested in production. NCP5220A = 0°C to 70° 1.7 mH, COUT1 = 3770 mF, A Symbol Test Conditions V5VDUAL − VBOOT − ...
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... Feedback Input Current Oscillator Frequency Oscillator Ramp Amplitude Minimum Duty Cycle Maximum Duty Cycle Soft−Start Pin Current for V1P5 Regulator 4. Guaranteed by design, not tested in production. NCP5220A = 0°C to 70° 1.7 mH, COUT1 = 3770 mF, A Symbol Test Conditions DVTTS0 IOUT 2.0 A (Sink Current) IOUT – ...
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... A Sourcing Current with 10 ms period and − pulse width − AMBIENT TEMPERATURE (°C) A Figure 7. VTT Source Current Load Regulation vs. Ambient Temperature NCP5220A 550 500 450 400 350 300 250 200 AMBIENT TEMPERATURE (°C) A Figure 4 ...
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... Channel 3: VTT output voltage, 1.0 V/div Channel 4: V1P5 output voltage, 1.0 V/div Time base: 10 ms/div Figure 11. S0−S5−S0 Transition NCP5220A Channel 1: SLP_S3 pin voltage, 5.0 V/div Channel 2: VDDQ output voltage, AC−coupled, 20 mV/div Channel 3: VTT output voltage, AC−coupled, 100 mV/div Channel 4: V1P5 output voltage, 50 mV/div Time base: 10 ms/div Figure 10. S0− ...
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... Time base: 1.0 ms/div Figure 15. V Source Current Transient, DDQ 0A−20A−0A NCP5220A Channel 1: Current sourced into of V1P5, 10 A/div Channel 2: VDDQ output voltage, AC−coupled, 100 mV/div Channel 3: VTT output voltage, AC−coupled, 50 mV/div Channel 4: V1P5 output voltage, AC−coupled, 100 mV/div Time base: 1.0 ms/div Figure 14 ...
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... General The NCP5220A 3−in−1 PWM Dual Buck Linear DDR Power Controller contains two high efficiency PWM controllers and an integrated two−quadrant linear regulator. The VDDQ supply is produced by a PWM switching controller with two external N−Ch FETs. The VTT termination voltage is an integrated linear regulator with sourcing and sinking current capability which tracks at one− ...
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... VDDQ with the internal gate drive power derived from 5VDUAL. While VTT output is connecting to the FBVTT pin directly, VTT voltage is designed to automatically track at the half of VDDQ. This regulator is NCP5220A stable with any value of output capacitor greater than 470 mF, and is insensitive to ESR ranging from 1 400 mW. ...
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... V UVLO = L and SLP_S3 = H. MCH ramps with SS pin, timing is 0 4.0 m (sec). VTT rises. 1 14. S0 Mode. 15. S5 Mode −− SLP_S5 = L. 16. DDQ, VTT and MCH Turned OFF. 17. S5 Mode. Figure 17. NCP5220A Power−Up and Power−Down NCP5220A Switching Frequency Doubles ...
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... SLP_S3 = 1 AND SLP_S5 = 1 AND _BOOTGD = 1 NOTE: 5VDUAL is assumed good conditions in any mode. All possible state transitions are shown. All unspecified inputs do not cause any state change. Figure 18. Transitions State Diagram of NCP5220A NCP5220A S5 SLP_S5 = 0 OR (SLP_S3 = 1 AND _BOOTGD = 0) S0 SLP_S3 = 0 AND SLP_S5 = 1 http://onsemi ...
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... The tradeoff is a corresponding increase in the input gate capacitor of the power MOSFETs. PCB Layout Considerations With careful PCB layout the NCP5220A can supply more of current very important to use wide traces or large copper shapes to carry current from the input node through the MOSFET switches, inductor and to the output filters and load ...
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... SW_DDQ 19 R2 BG_DDQ 2 TG_DDQ 17 BOOT 5VDUAL 15 COMP_1P5 14 R4 SLP_S3 TG_1P5 12 BG_1P5 11 GND_1P5 Figure 19. Charge Pump Circuit at BOOT Pin NCP5220A 5VDUAL TP2 D1 BAT54HT1 100 nF Q2 NTD40N03 3 L VDDQ 4 C6 DPAK 4 NTD40N03 3 http://onsemi.com 15 TP5 2.5 VDDQ + + C7 C25 ...
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... NCP5220A Figure 20. NCP5220A Typical Application Circuit http://onsemi.com 16 ...
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... Table 2. Bill of Material of NCP5220A Application Circuit Reference Design Description Q1, Q2 Power MOSFET N−Channel Q3, Q4 Power MOSFET N−Channel D1, D2 Rectifier Schottky Diode U1 Controller Zener Zener Diode L1 Toroidal Choke L2, L3 Toroidal Choke C2, C3 Aluminum Electrolytic Capacitor C5 Aluminum Electrolytic Capacitor C21 Aluminum Electrolytic Capacitor ...
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... COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A2 0.65 0.75 A3 0.20 REF b 0.23 0.28 D 6.00 BSC D2 3.98 4.28 E 5.00 BSC E2 2.98 3.28 e 0.50 BSC K 0.20 −−− L 0.50 0.60 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCP5220A/D ...