sc4524d Semtech Corporation, sc4524d Datasheet - Page 14

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sc4524d

Manufacturer Part Number
sc4524d
Description
18v 2a Step-down Switching Regulator
Manufacturer
Semtech Corporation
Datasheet
Applications Information (Cont.)
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
Therefore, the procedure of the voltage loop design for
the SC4524D can be summarized as:
(1) Plot the converter gain, i.e. control to feedback transfer
function.
(2) Select the open loop crossover frequency, F
10% and 20% of the switching frequency. At F
required compensator gain, A
ceramic output capacitors, the ESR zero is neglected and
the required compensator gain at F
(3) Place the compensator zero, F
20% of the crossover frequency, F
(4) Use the compensator pole, F
F
(5) Then, the parameters of the compensation network
can be calculated by
Z
.
-60
-60
-30
-30
60
60
30
30
0
0
1K
1K
R
R
C
C
C
C
A
A
A
A
V
V
V
V
7
7
o
o
Figure 8. Bode plots for voltage loop design
C
C
C
C
5
5
8
8
c
c
=
=
=
=
=
=
=
=
=
=
=
=
. 0
. 0
1 (
1 (
2
2
2
2
⋅ π
⋅ π
⋅ π
⋅ π
20
20
20
20
28
28
+
+
10
10
Fp
Fp
16
16
600
600
/ s
/ s
15
15
log
log
log
log
10
10
20
20
10K
10K
G
G
R
9 .
9 .
R
A
A
C
C
G
C
C
ω
ω
V
V
10
10
PWM
PWM
7
o
c
PWM
7
C
C
5
8
5
8
p
p
 
 
10
10
1 ( )
1 ( )
3
3
=
=
=
=
=
=
G
G
28
28
=
=
=
Fz1
Fz1
3
3
1
1
1 (
1 (
=
=
CA
CA
10
1
1
. 0
1 (
2
2
2
3
3
2
1
1
+
+
g
FREQUENCY (Hz)
FREQUENCY (Hz)
22
22
22
22
⋅ π
R
R
π
20
20
28
⋅ π
π
+
+
6
6
G
+
m
/ s
/ s
10
22
22
A
20
F
F
S
S
C
1 .
1 .
CA
1
R s
R s
16
1
600
/ s
.
.
1 .
1 .
1 Z
P
1
1
k 3
k 3
1
C
R
ω
ω
15
1 .
1 .
. In typical applications with
log
log
10
20
2
2
Fc
Fc
100K
100K
ESR
ESR
R
R
G
n
n
9 .
10
10
R
ω
π
π
10
10
P1
Q
Q
10
7
7
PWM
S
p
F
F
10
10
 
C
C
1
1
, to cancel the ESR zero,
10
C
1 ( )
3
,
+
+
C
C
.
G
28
3
3
O
O
3
3
3
C
C
Z1
C
1
s
s
Fp1
Fp1
=
1 (
)
)
CA
1
3
3
Fz
Fz
3
=
=
can be estimated by
O
O
, between 10% and
1
+
2
2
22
22
R
2
2
=
=
. 0
. 0
+
/
/
6
/ s
22
S
⋅ π
⋅ π
12
12
V
V
ω
ω
Fsw/2
Fsw/2
1 .
R s
V
V
45
45
.
1 .
1
FB
FB
k 3
O
O
2
2
n
n
ω
1M
1M
1 .
80
80
pF
pF
2
ESR
)
)
nF
nF
n
10
 
 
ω
10
π
Q
p
F
10
C
1
C
+
10
10
C
, between
3
C
O
3
C
, find the
s
3
)
(9)
1
1
R
=
O
2
3
3
1
C
2
=
. 0
/
O
⋅ π
22
22
12
ω
V
V
45
,
FB
n
O
2
10M
10M
80
pF
)
nF
10
10
 
10
6
6
where g
Example: Determine the voltage compensator for an
800kHz, 12V to 3.3V/2A converter with 22uF ceramic
output capacitor.
Choose a loop gain crossover frequency of 80kHz, and
place voltage compensator zero and pole at F
(20% of F
required compensator gain at F
Then the compensator parameters are
Select R
Compensator parameters for various typical applications
are listed in Table 5. A MathCAD program is also available
upon request for detailed calculation of the compensator
parameters.
Thermal Considerations
For the power transistor inside the SC4524D, the
conduction loss P
circuit loss P
where V
1
3
1
1
3
3
ω
22
0 .
0 .
3 .
3 .
Z
=
A
A
P
P
P
P
P
P
P
P
P
P
P
P
=
=
C
C
10
R
C
C
BST
BST
D
D
IND
IND
TOTAL
TOTAL
SW
SW
7
BST
m
=12.4k, C
15
15
R
R
ESR
=0.3mA/V is the EA gain of the SC4524D.
C
C
C
C
=
=
=
=
1
is the BST supply voltage and t
20
20
5
5
=
=
C
7
7
8
8
=
=
=
=
6
D
D
1 (
1 (
), and F
9 .
9 .
C
BST,
=
=
1
1
1 (
1 (
2
2
D
D
log
log
O
dB
dB
2
2
0.3
0.3
1
2
2
V
V
3
P
P
1 .
1 .
,
can be estimated as follows:
10
10
CESAT
CESAT
18.5
18.5
C
C
) D
) D
0 .
3 .
t
t
V
V
S
S
BST
BST
16
16
~
~
600
600
+
+
11.4
11.4
10
10
C
5
20
20
=1nF, and C
, the switching loss P
5.5
5.5
1
1
P
P
V
V
1
1
V
V
=
10
10
D
D
3 .
3 .
P1
SW
SW
IN
IN
3
3
I
I
15
10
10
10
10
40
40
O
O
=600kHz. From Equation (9), the
I
I
3
3
I )
I )
1
1
O
O
I
I
1
1
3
3
+
+
3
3
I
I
O
O
1
1
9 .
1
1
O
O
2
2
O
O
2
2
P
P
2
2
2
2
1
1
4 .
4 .
dB
4 .
4 .
BST
BST
2
2
F
F
R
R
80
80
k
k
4 .
4 .
SW
SW
10
10
DC
DC
10
10
+
+
10
10
8
3
3
=22pF for the design.
1
1
3
3
C
P
P
3
3
22
22
is
Q
Q
0.8nF
0.8nF
10
10
2
2
P
P
1
1
6
6
pF
pF
Q
Q
1.0
1.0
3.3
3.3
SW
=
=
S
is the equivalent
, and bootstrap
V
V
IN
IN
11.4dB
11.4dB
2
2
mA
mA
(10)
Z1
=16kHz
14

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