ml4803cs-2 Microsemi Corporation, ml4803cs-2 Datasheet - Page 7

• Manufacturer Part Number: ml4803cs-2
• Description: 8-pin Controller Combo
• Manufacturer: Microsemi Corporation

LEADING/TRAILING MODULATION
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 2 shows a typical trailing edge
control scheme.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation is
determined during the OFF time of the switch. Figure 3
shows a leading edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns OFF
and Switch 2 (SW2) turns ON at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the first
stage is reduced. Calculation and evaluation have shown
that the 120Hz component of the PFC’s output ripple
voltage can be reduced by as much as 30% using this
method, substantially reducing dissipation in the high-
voltage PFC capacitor.
TYPICAL APPLICATIONS
ONE PIN ERROR AMP
The ML4803 utilizes a one pin voltage error amplifier in
the PFC section (VEAO). The error amplifier is in reality a
current sink which forces 35µA through the output
+
DC
VIN
REF
OSC
I1
L1
U4
+
–
EA
RAMP
CLK
U3
Figure 3. Typical Leading Edge Control Scheme.
VEAO
SW2
SW1
+
–
February 1999
CMP
U1
I2
C1
(Continued)
I4
I3
D
R
DFF
CLK
U2
RL
Q
Q
programming resistor. The nominal voltage at the VEAO
pin is 5V. The VEAO voltage range is 4 to 6V. For a
11.3MW resistor chain to the boost output voltage and 5V
steady state at the VEAO, the boost output voltage would
be 400V.
PROGRAMMING RESISTOR VALUE
Equation 1 calculates the required programming resistor
value.
PFC VOLTAGE LOOP COMPENSATION
The voltage-loop bandwidth must be set to less than
120Hz to limit the amount of line current harmonic
distortion. A typical crossover frequency is 30Hz.
Equation 1, for simplicity, assumes that the pole capacitor
dominates the error amplifier gain at the loop unity-gain
frequency. Equation 2 places a pole at the crossover
frequency, providing 45 degrees of phase margin.
Equation 3 places a zero one decade prior to the pole.
Bode plots showing the overall gain and phase are shown
in Figures 5 and 6. Figure 4 displays a simplified model of
the voltage loop.
Rp
C
C
C
COMP
COMP
COMP
V
RAMP
VSW1
BOOST
=
=
113
R
16
VEAO
p
I
.
PGM
nF
M
V
W
BOOST
V
´
EAO
400
V
400
´
TIME
TIME
VEAO C
0 5
.
35
V
Pin
V
300
´
A
50
220
.
W
OUT
V
m
F
´
113
2
.
ML4803
2
M
´ ´
p
f
30
2
Hz
(1)
(2)
2
7