tc5747 ETC-unknow, tc5747 Datasheet - Page 20

• Manufacturer Part Number: tc5747
• Description: Single Chip Cmos Imager With Integrated Image Signal Processor Jpeg Codec
• Manufacturer: ETC-unknow

TC5747 Data Sheet
Single Chip CMOS Imager
4.1.2
The bus master, typically the host
START condition, and passes the address of the requested device along with the type of access (read or
write bit – the MSB or the start byte). The requested device replies with an acknowledge (ACK). The host
can then perform as many transactions as it wishes, until the host activates a STOP condition. The bus is
considered free after the STOP condition.
The data on the
below. Only the host may change the data while
condition, and a low-to-high a STOP condition.
The master device activates a
address, and a direction bit (
the SDA line as acknowledge procedure.
The TC5747 expects the first two bytes after the address byte to be the register address of the first register
that is to be read or written by the host. Programming is done in host commands level which is translated
into a series of register level commands.
When writing registers to the TC5747, the following bytes are data bytes. The data for each READ or
WRITE access is two bytes long. The TC5747 performs auto increment until the STOP condition is
identified. Auto increment is not performed when the initial address is in the address space that is allocated
to the On-Chip-Memories. This address space is reserved for tables, where multiple bytes are written to a
single address.
When reading registers from the TC5747, the register address (2 bytes) should be followed by a repeated
START condition, device address, and
(data).
The sequence of loading or reading registers is described in the figure below.
The colored boxes represent host-to-slave data transfer.
The clear boxes represent slave-to-host data transfer.
Mode of Operation
SDA
pin must be stable during the high period of the clock (
Figure 4: I
R/W#
START
, 1 for read, 0 for write). The addressed device answers by pulling down
DSP
2
, initiates an access to the TC5747 device. The bus master activates a
C Interface START and STOP Conditions
condition, and sends the first byte of data that contains the 7-bit
R/W#
Figure 5: I
bit equal to 1, to change mode from write (address) to read
TransChip
SCL
14
2
C Protocol
is high. A high-to-low transition marks a START
SCL
) as shown in the figure