ip2005a International Rectifier Corp., ip2005a Datasheet
ip2005a
Available stocks
Related parts for ip2005a
ip2005a Summary of contents
Page 1
... Optimized LGA Power Stage Integrated Power Semiconductors, Driver IC, & Passives = 95ºC Description The iP2005A is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 7 ...
Page 2
... Input Voltage ( Output Voltage (V ) OUT Output Current (I ) OUT Switching Frequency On Time Duty Cycle Minimum V On Time SW Block Temperature (T ) BLK www.irf.com ) MIN TYP MAX 4.5 - 7.0 6 250 - 1500 - - -40 - 125 2/8/2008 PD-60325 iP2005APbF UNITS CONDITIONS kHz % 5.0V 12V DD IN ºC (Note 2) 2 ...
Page 3
... PD-60325 iP2005APbF UNITS CONDITIONS V = 12V 5.0V 1.3V, I OUT OUT 1MHz 0.3uH, T OUT BLK (Note 5.0, ENABLE = 12V, ENABLE = 1MHz, 10 µF Ceramic, X5R, 16V ...
Page 4
... Not associated with rise and fall times. Does not affect Power Loss www.irf.com = 0ºC to 125ºC and V = 5.0V unless otherwise specified. BLK DD MIN TYP MAX - - 0.8 2 100 - - 100 - - 2/8/2008 PD-60325 iP2005APbF UNITS CONDITIONS Schmitt Trigger Input V = POR to 7.0V kΩ DD (Note ...
Page 5
... Power Loss Curve SOA Curve www.irf.com Figure 1 Power Loss Curve Figure 2 Safe Operating Area Curve 2/8/2008 PD-60325 iP2005APbF 5 ...
Page 6
... OUT SW 1.0 1 125ºC BLK BLK 0.7 1.0 0.5 0.2 0.9 0.0 0.8 -0.2 -0.5 0.7 -0.7 -1.0 0.6 0.6 0.7 0.8 250 Figure 6 Normalized Power Loss vs. Switching Frequency Supply Current vs. Switching Frequency DD 2/8/2008 PD-60325 iP2005APbF = 12. 5. 40A OUT = 1MHz SW = 300nH = 125ºC 1.3 1.8 2.3 2.8 Output Voltage (V) = 12.0V = 5.0V = 1.3V = 40A = 300nH = 125ºC 500 750 1000 1250 Switching Frequency (kHz) 4.2 3.7 3.3 2.8 2.3 1 ...
Page 7
... Figure 8 Power Loss Test Circuit Figure 9 Timing Diagram 2/8/2008 PD-60325 iP2005APbF 7 ...
Page 8
... Current). The point at which the horizontal line meets the Y-axis is the SOA continuous current 12. 5. 1.3V OUT F = 1MHz 300nH OUT Figure 10 SOA Example, Continuous current ≈ 31A for T www.irf.com axis intercept to the SOA curve. X PCB 2/8/2008 PD-60325 iP2005APbF = 100ºC & 110ºC CASE 8 ...
Page 9
... To calculate Power Loss for a given set of operation conditions, the following procedure should be followed: Power Loss Procedure 1.Determine the maximum current for each iP2005A and obtain the maximum power loss from Figure 1 2.Use the normalized curves to obtain power loss values that match the operating conditions in the application 3 ...
Page 10
... SOA temperature adjustment for output voltage ≈ 0.0ºC SOA temperature adjustment for output inductor ≈ 0.6 ºC SOA temperature adjustment for switch frequency ≈ -3.5 ºC = 110ºC CASE axis intercept to the SOA curve. X axis by adding or subtracting the SOA adjustment X intercept point. X 2/8/2008 PD-60325 iP2005APbF decrease of 4.1º ...
Page 11
... Vsw of iP2003A The iP2005A is designed for low Electromagnetic Interference (EMI) which minimizes power loss and space, and simplifies system design by eliminating the need for external snubber circuits. These benefits are achieved by optimizing the internal component layout, integrating bypass filters and implementing active clamp circuitry as a means of reducing switching node voltage ringing ...
Page 12
... When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the Control and Synchronous FETs are turned off. Output of internal regulator. Attached a minimum of 1.0µF capacitance from this pin to PGND. Recommended to use 16V, X5R, Ceramic type capacitor. 2/8/2008 PD-60325 iP2005APbF 12 ...
Page 13
... Recommended PCB Layout Figure 12 Top copper and Solder-mask layer of PCB layout www.irf.com 2/8/2008 PD-60325 iP2005APbF 13 ...
Page 14
... PCB Layout Guidelines The following guidelines are recommended to reduce the parasitic values and optimize overall performance. • All pads on the iP2005A footprint design need to be Solder-mask defined (see Figure 12). Also refer to International Rectifier application notes AN1028 and AN1029 for further footprint design guidance. ...
Page 15
... Layout Notes Land patterns on user’s PCB should be an identical mirror image of the pattern shown in bottom view 2. Lands should be solder mask defined 3. All I/O pads on this product are metal finish with flash gold Figure 14 Mechanical Outline Drawing 2/8/2008 PD-60325 iP2005APbF BOTTOM VIEW 15 ...
Page 16
... Tape and Reel Information YYMM XXXX 2005AP www.irf.com YYMM XXXX 2005AP XX XX 12.00 (.473) FEED DIRECTION Figure 15 Tape and Reel Information 2/8/2008 PD-60325 iP2005APbF 16.00 (.630) 16 ...
Page 17
... Solid lines show PCB pad openings. 5.The recommended reflow peak temperature is 260ºC. The total furnace time is approximately 5 minutes with approximately 10 seconds at peak temperature. Part Marking www.irf.com Figure 16 Solder Paste Stencil Design Figure 17 Part Marking 2/8/2008 PD-60325 iP2005APbF 17 ...
Page 18
... N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105 This product has been designed for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 12/24/2007 2/8/2008 PD-60325 iP2005APbF TAC Fax: (310) 252-7903 18 ...