ip2005c International Rectifier Corp., ip2005c Datasheet - Page 10

• Manufacturer Part Number: ip2005c
• Description: Synchronous Buck Optimized Lga Power Block
• Manufacturer: International Rectifier Corp.

Internal Block Diagram
Pin Description
Notes:
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Pin Number
7,8
1
2
3
4
5
6
A. It is recommended to connect PIN 7 and 8 to PIN 1 on PCB to reduce thermal resistance.
Pin Name
ENABLE
PGND
PWM
V
N/C
V
V
SW
DD
IN
FET is on and the Sync FET is off. When PWM is LOW, the Sync FET
TTL level input to MOSFET drivers. When PWM is HIGH, the Control
When set to logic level high, internal circuitry of the device is enabled.
Figure 12 Internal Block Diagram
When set to logic level low, the Control and Synchronous FETs are
Voltage Switching Node – pin connection to the output inductor.
04/09/2009
Input voltage pin. Connect input capacitors close to this pin.
No Connection, can be left floating. (Note A)
Supply voltage to internal circuitry.
is on and the Control FET is off.
Power Ground
Description
turned off.
iP2005CPbF
PD-60360
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