sc4608mltrt Semtech Corporation, sc4608mltrt Datasheet - Page 8

• Manufacturer Part Number: sc4608mltrt
• Description: High Efficiency Synchronous Step Down Controller
• Manufacturer: Semtech Corporation

Enable
The SC4608 is enabled by applying a voltage greater than
2.7 volts to the AV
AV
tion is invoked by clamping the EN pin to a voltage below
0.3*AV
AV
high side and low side MOSFETs are turned off and the
internal soft start voltage is held low.
Oscillator
The FSET pin is used to set the PWM oscillator frequency
through an external timing capacitor that is connected
from the FSET pin to the GND pin. The resulting ramp
waveform ion the FSET pin is a triangle at the PWM fre-
quency with a peak voltage of 1.3V and a valley voltage
of 0.3V. 160ns minimum OFF time for the top switch
allows the bootstrap capacitor to be charged during each
cycle. The capacitor tolerance adds to the accuracy of
the oscillator frequency. The approximate operating fre-
quency and soft start time are both determined by the
value of the external timing capacitor as shown in Table
1.
Synchronous mode operation is invoked by using a sig-
nal from an external clock. A low value resistor (100
typical) must be inserted in series with the timing capaci-
tor between the timing capacitor and the GND pin. The
other terminal of the timing capacitor will remain con-
nected to the FSET pin. The transformed external clock
signal is then connected to the junction of the external
timing capacitor and the added resistor R
in Figure 1.
POWER MANAGEMENT
Application Information
Value of the External Timing Capacitor Placed Across
2007 Semtech Corp.
DD
DD
Table 1. Operating Frequency value Based on the
C
pin during sleep mode. During the sleep mode, the
falls below 2.35 volts or when sleep mode opera-
a
E
p
DD
x
a
e t
. 0.1µA is the typical current drawn through the
i c
r
o t
n
4
1
2
5
l a
r
7
7
6
2
V
0
0
0
0
i T
a
the FSET and GND Pins
u l
m
DD
e
n i
pin. The SC4608 is disabled when
p (
g
F
)
F
e r
q
u
e
1
5
3
2
n
0
7
5
9
c
0
SYNC
5
0
5
y
0
k (
as shown
H
) z
8
The maximum frequency of the external clock signal can
be higher than the natural switching frequency by about
10%.
External
External
Clock
Clock
Signal
Signal
UVLO
When the EN pin is not pulled and held below 0.3*AV
the voltage on the AV
the SC4608. As AV
block senses AV
MOSFETs off and the internal soft start voltage low until
AV
will initiate a soft start when AV
esis (350mV) in the UVLO comparator provides noise im-
munity during its start up.
Power Good Indicator
The PGOOD pin is the open-drain output of the power
good comparators. These comparators are incorporated
with small amount of hysteresis. A pull-up resistor from
the PGOOD pin to the input supply or the output sets the
logic high level of the PGOOD signal. The VSENSE low-to-
high trip voltage of the power good comparator is 89%
of the final regulation voltage. The power good compara-
tor output becomes valid provided that V
±11% of the programmed output voltage. In shutdown
mode the power good output is actively pulled low. The
PGOOD signal delay depends on its operating frequency
fs, for example, about 14ms@ fs=575kHz and 24ms @
fs=330kHz.
Soft Start
The soft start function is required for step down control-
lers to prevent excess inrush current through the DC bus
during start up. Generally this can be done by sourcing a
controlled current into a timing capacitor and then using
the voltage across this capacitor to slowly ramp up the
error amp reference. The closed loop creates narrow
DD
reaches 2.7V. If no faults are present, the SC4608
56pF
56pF
C
C
DD
DD
and keeps the high side and low side
increases during start up, the UVLO
D
D
DD
Figure 1
pin determines the operation of
1k
1k
R
R
C
C
100
100
R
R
FSET
FSET
SYNC
SYNC
DD
exceeds 2.7V. A hyster-
A
A
FSET
FSET
O
SC4608
www.semtech.com
is within about
SC4608
SC4608
DD
,