bd8918fv ROHM Co. Ltd., bd8918fv Datasheet - Page 9

• Manufacturer Part Number: bd8918fv
• Description: Ic Card Interface Ics With Built-in Low Noise Ldo Regulator
• Manufacturer: ROHM Co. Ltd.

© 2009 ROHM Co., Ltd. All rights reserved.
BD8918F,BD8918FV,BD8919F,BD8919FV
www.rohm.com
3-3) Activation sequence
[Activation sequence under different RSTIN input timings]
When OFFB is in the “High” state and the CMDVCCB signal from the controller turns from H to L, the activation sequence
starts to activate each functional block in the following order:
The RST outputs signals based on the RSTIN input, being reset approximately 472sec after the CMDVCCB signal turns
from H to L. The RSTIN input becomes effective approximately 48s after I/O TRANS turns ON. If RSTIN becomes Lo
after RSTIN becomes effective and the RST output is released, the CLK signal is output. If RSTIN is High when the RST
output is released, the CLK signal is output as soon as the RST output is released. (Refer to Fig. 4-1, 4-2 and 4-3)
(RSTIN input sequence not specified by ISO7816)
CMDVCCB
LDO ON
I/O TRANS ON
CLK BUF ON
RST BUF ON
CMDVCCB
RSTIN
VCC
IO_C
IO_U
CLK
RST
RSTIN

__________________________________________________

 (RSTINAlways High)


VCC
IO_C
RST
IO_U
CLK
Fig. 4-1 Activation sequence 1
Fig. 4-3 Activation sequence 3
t0
(VCC output)
t0
t1
t1
t2 t3
t2 t3
(IO_C, IO_U Bus: Pull-up)
(RST release)
(CLK output)
Min:200ns
t4= tact
t4= tact
ART
ART
9/15
CLK, RST BUF ON (CLK output, RST release)
t1: LDO startup time
t2: I/O ON time
t3: CLK output release time (t3-t2)
t4: RST release time
481s
(Activation time)
CMDVCCB
RSTIN
 When RSTIN remains High until RST is released
 (RSTIN=Always High)

VCC
IO_C
RST
IO_U
Fig.6-3 立ち上げシーケンス 3
CLK
Fig. 4-2 Activation sequence 2
t0
t1
t2
t3
t4= tact
= typ. 24µs
= typ. 424µs
= Min. 200ns
= typ,472µs,
Technical Note
2010.4 - Rev.D
ART
max.