at91sam9g15-cu ATMEL Corporation, at91sam9g15-cu Datasheet - Page 10

• Manufacturer Part Number: at91sam9g15-cu
• Description: At91sam Arm-based Embedded Mpu
• Manufacturer: ATMEL Corporation

4.2.1
10
SAM9G15
Reset State
In the tables that follow, the column “Reset State” indicates the reset state of the line with
mnemonics.
Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned,
the PIO Line is maintained in a static state as soon as the reset is released. As a result, the bit
corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released.
Indicates whether the signal is input or output state.
Indicates whether Pull-Up, Pull-Down or nothing is enabled.
Indicates if Schmitt Trigger is enabled.
Note:
Table 4-2.
• “PIO” “/” signal
• “I”/”O”
• “PU”/”PD”
• “ST”
I/O Type
USBFS
USBHS
CLOCK
DIB
Example:
configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”.
That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address
line 20 with Pull-Down.
I/O Frequency
SAM9G15 I/O Type Assignment and Frequency (Continued)
(MHz)
The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is
480
12
50
25
Charge Load
(pF)
10
10
50
25
Current
Output
HFSDPA, HFSDPB/DFSDP, HFSDPC, HFSDMA,
HHSDPA, HHSDPB/DHSDP, HHSDMA,
HFSDMB/DFSDM, HFSDMC
XIN, XOUT, XIN32, XOUT32
HHSDMB/DHSDM
Signal Name
DIBN, DIBP
11052AS–ATARM–27-Jul-11