at91sam9x25-cu ATMEL Corporation, at91sam9x25-cu Datasheet
at91sam9x25-cu
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at91sam9x25-cu Summary of contents
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Features • Core ® – ARM926EJ-S™ ARM Thumb – 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit • Memories – One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, ® SDCard, DataFlash or serial DataFlash. ...
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Description The SAM9X25 is a high-performance ARM926-based embedded microprocessor unit, running at 400 MHz and featuring multiple networking/connectivity peripherals, optimized for industrial applications such as building automation, gateways and medical. The SAM9X25 features two 2.0A/B compatible Controller Area Network ...
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Block Diagram Figure 2-1. SAM9X25 Block Diagram 11054AS–ATARM–29-Jul-11 PIO PIO SAM9X25 3 ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0-PCK1 Programmable Clock ...
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Table 3-1. Signal Description List (Continued) Signal Name Function D0-D15 Data Bus D16-D31 Data Bus A0-A25 Address Bus NWAIT External Wait Signal NCS0-NCS5 Chip Select Lines NWR0-NWR3 Write Signal NRD Read Signal NWE Write Enable NBS0-NBS3 Byte Mask Signal NFD0-NFD16 ...
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Table 3-1. Signal Description List (Continued) Signal Name Function Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock TXDx USARTx Transmit Data RXDx USARTx Receive Data RTSx USARTx Request To Send CTSx USARTx Clear To Send UTXDx UARTx ...
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Table 3-1. Signal Description List (Continued) Signal Name Function PWM0-PWM3 Pulse Width Modulation Output HFSDPA USB Host Port A Full Speed Data + HFSDMA USB Host Port A Full Speed Data - HHSDPA USB Host Port A High Speed Data ...
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Table 3-1. Signal Description List (Continued) Signal Name Function ERX0-ERX1 Receive Data ERXER Receive Error EMDC Management Data Clock EMDIO Management Data Input/Output AD0-AD11 12 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference CANRXx CAN input CANTXx CAN output DIBN ...
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Package and Pinout The SAM9X25 is available in 217-ball BGA package. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. 4.2 I/O Description Table 4-1. I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI EBI_O EBI_CLK RSTJTAG SYSC VBG ...
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When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the Pin Description table. Table 4-2. I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI EBI_O EBI_CLK RSTJTAG SYSC VBG USBFS USBHS CLOCK DIB 4.2.1 Reset State ...
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Indicates if Schmitt Trigger is enabled. Note: 11054AS–ATARM–29-Jul-11 Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state ...
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BGA Package Pinout Table 4-3. Pin Description BGA217 Ball Power Rail I/O Type Signal L3 VDDIOP0 GPIO PA0 P1 VDDIOP0 GPIO PA1 L4 VDDIOP0 GPIO PA2 N4 VDDIOP0 GPIO PA3 T3 VDDIOP0 GPIO PA4 R1 VDDIOP0 GPIO PA5 ...
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Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal C5 VDDANA GPIO_ANA C1 VDDANA GPIO_ANA B2 VDDANA GPIO_ANA PB10 A3 VDDANA GPIO_ANA PB11 B4 VDDANA GPIO_ANA PB12 A2 VDDANA GPIO_ANA PB13 C4 VDDANA GPIO_ANA PB14 C3 VDDANA ...
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Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal P13 VDDNF EBI PD0 R14 VDDNF EBI PD1 R13 VDDNF EBI PD2 P15 VDDNF EBI PD3 P12 VDDNF EBI PD4 P14 VDDNF EBI PD5 N14 VDDNF EBI PD6 ...
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Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal T17 VDDUTMIC POWER VDDUTMIC T16 GNDUTMI GND GNDUTMI D14 VDDIOM EBI D15 VDDIOM EBI A16 VDDIOM EBI B16 VDDIOM EBI A17 VDDIOM EBI B15 VDDIOM EBI C14 VDDIOM ...
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Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal A8 VDDIOM EBI_O NWR3 D11 VDDIOM EBI_CLK SDCK C11 VDDIOM EBI_CLK #SDCK B12 VDDIOM EBI_O SDCKE B11 VDDIOM EBI_O RAS C10 VDDIOM EBI_O CAS A12 VDDIOM EBI_O SDWE ...
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Power Considerations 5.1 Power Supplies The SAM9X25 has several types of power supply pins. Table 5-1. SAM9X25 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 ...
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Processor and Architecture 6.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • ...
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... APB/AHB bridge The AT91SAM9X25 product embeds two separated APB/AHB bridges. This architecture enables to make concurrent access on both bridge. Each peripheral can be clocked at a lower speed (MCK divided clock) in order to decrease the current consumption. 6.3 Bus Matrix • 12-layer Matrix, handling requests from 11 masters • ...
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... Master 2&3 Master 4&5 Master 6 Master 7 Master 8 Master 9 Master 10 Master 11 6.5 Matrix Slaves The Bus Matrix of the AT91SAM9X25 product manages 9 slaves. Each slave has its own arbi- ter, allowing a different arbitration per slave. Table 6-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 ...
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... All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. AT91SAM9X25 Master to Slave Access Table 6-3. Masters ...
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... USB The AT91SAM9X25 features the following USB communication ports: • 2 Hosts (A and B) High Speed (EHCI) and Full Speed (OHCI) • 1 Host (C) Full Speed only (OHCI) • 1 Device High Speed The High Speed USB Host Port A is shared with the High Speed USB Device port and con- nected to the second UTMI transceiver ...
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DMA Controller 0 • Two Masters • Embeds 8 channels • 64-byte FIFO for channel 0, 16-byte FIFO for Channel • features: – Linked List support with Status Write Back operation at End of Transfer – ...
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DMA Controller 1 • Two Masters • Embeds 8 channels • 16-byte FIFO per Channel • features: – Linked List support with Status Write Back operation at End of Transfer – Word, HalfWord, Byte transfer support. – Peripheral to ...
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Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug ...
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Memories Figure 7-1. SAM9X25 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 EBI 256 MBytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 256 MBytes DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF ...
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Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 ...
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Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode ...
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System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure ...
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Figure 8-1. SAM9X25 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC 12M RC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset ...
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Chip Identification • Chip ID: 0x819A_05A1 • Chip ID Extension: 4 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 8.2 Backup Section The SAM9X25 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • ...
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Peripherals 9.1 Peripheral Mapping As shown in space between the addresses 0xF000 0000 and 0xFFFF C000. Each User Peripheral is allocated 16 Kbytes of address space. 9.2 Peripheral Identifiers Table 9-1 for the control of the peripheral interrupt with ...
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Table 9-1. Instance 9.3 Peripheral Signal Multiplexing on I/O Lines The SAM9X25 features 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral ...
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Embedded Peripherals 10.1 Serial Peripheral Interface (SPI) • Two SPIs • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire ...
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MSB- or LSB-first – Optional break generation and detection – by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester ...
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Serial Synchronous Controller (SSC) • One SSC • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I • Contains an independent receiver and transmitter and a common clock divider ...
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High Speed USB Host Port (UHPHS) • Compliant with EnhancedHCI Rev 1.0 Specification – Compliant with USB V2.0 High-speed and Full-speed Specification – Supports Both High-speed 480Mbps and Full-speed 12 Mbps USB devices • Compliant with OpenHCI Rev 1.0 ...
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Ethernet 10/100 MAC (EMAC) • Two EMACs • EMAC0 supports MII Mode • EMAC1 supports RMII Mode only • Compatibility with IEEE Standard 802.3 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operations ...
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Unaligned system address to data transfer width supported in hardware – Picture-In-Picture Mode (on DMAC0 only) • Channel Buffering – 16-word FIFO (64-word for channel 0 of DMAC0) – Automatic packing/unpacking of data to fit FIFO width • Channel ...
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Pulse Width Modulation Controller (PWM) • 4 channels, one 32-bit counter per channel • Common clock generator, providing Thirteen Different Clocks – A Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter ...
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Mechanical Overview Figure 11-1. 217-ball BGA Package Drawing 11054AS–ATARM–29-Jul-11 SAM9X25 41 ...
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Table 11-1. Device and 217-ball BGA Package Maximum Weight 450 Table 11-2. 217-ball BGA Package Characteristics Moisture Sensitivity Level Table 11-3. Package Reference JEDEC Drawing Reference JESD97 Classification Table 11-4. Soldering Information Ball Land Solder Mask Opening SAM9X25 42 mg ...
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... SAM9X25 Ordering Information Table 12-1. SAM9X25 Ordering Information Ordering Code AT91SAM9X25-CU 11054AS–ATARM–29-Jul-11 Package Package Type BGA217 Green SAM9X25 Temperature Operating Range Industrial -40°C to 85°C 43 ...
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SAM9X25 44 11054AS–ATARM–29-Jul-11 ...
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... Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, DataFlash®, SAM-BA® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM®, the ARMPowered® logo, Thumb® and others are the registered trademarks or trademarks of ARM Ltd ...