at80f52 ATMEL Corporation, at80f52 Datasheet
at80f52
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at80f52 Summary of contents
Page 1
... The on-chip QuickFlash allows custom codes to be quickly programmed in the factory. By combining a versatile 8-bit CPU with Quick- Flash on a monolithic chip, the Atmel AT80F52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control appli- cations ...
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... Block Diagram V CC GND RAM ADDR. REGISTER B REGISTER PSEN TIMING ALE INSTRUCTION AND REGISTER EA CONTROL RST OSC AT80F52 3-16 P0.0 - P0.7 PORT 0 DRIVERS PORT 0 PORT 2 RAM LATCH LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT 1 LATCH PORT 1 DRIVERS P1.0 - P1.7 P2.0 - P2.7 PORT 2 DRIVERS ...
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... QuickFlash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt archi- tecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT80F52 is designed with static logic for operation down to zero frequency and sup- ports two software selectable power saving modes. The ...
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... PSEN Program Store Enable is the read strobe to external pro- gram memory. When the AT80F52 is executing code from external pro- gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. ...
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... When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Data Memory The AT80F52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space ...
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... Timer 0 and 1 Timer 0 and Timer 1 in the AT80F52 operate the same way as Timer 0 and Timer 1 in the AT89C51. Timer 2 Timer 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). ...
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Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit ...
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... C/ PIN Figure 4. Timer 2 in Baud Rate Generator Mode NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 ÷ 2 OSC C/ C/ PIN TRANSITION DETECTOR T2EX PIN AT80F52 3-22 (DOWN COUNTING RELOAD VALUE) 0FFH 0FFH OVERFLOW TH2 TL2 CONTROL TR2 RCAP2H RCAP2L (UP COUNTING RELOAD VALUE) TH2 ...
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Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the ...
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... Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. UART The UART in the AT80F52 operates the same way as the UART in the AT89C52. Interrupts The AT80F52 has a total of six interrupt vectors: two exter- nal interrupts (INT0 and INT1), three timer interrupts (Tim- ers 0, 1, and 2), and the serial port interrupt ...
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Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz crystal or ceramic resonator may be used. ...
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... Program Memory Lock Bits The AT80F52 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table. Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 Protection Type program lock features ...
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... A CC Symbol Parameter 1/t Oscillator Frequency CLCL t Address to Data Valid AVQV t ENABLE Low to Data Valid ELQV t Data Float After ENABLE EHQZ QuickFlash Verification Waveforms P1.0 - P1.7 P2.0 - P2.4 (ENABLE) AT80F52 ADDR. P1 OOOOH/1FFFH P2 A12 P2.6 P2.7 VERIFICATION P3.6 MODES TABLE P3.7 XTAL 2 3-20 MHz XTAL1 GND VERIFICATION ADDRESS t DATA OUT PORT 0 ...
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... Port Ports Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power Down is 2V. CC AT80F52 3-28 *NOTICE: = -40°C to 85° C and Condition (Except EA) (Except XTAL1, RST) (XTAL1, RST ...
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AC Characteristics Under operating conditions, load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. External Program and Data Memory Characteristics Symbol Parameter 1/t Oscillator Frequency CLCL t ALE Pulse ...
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... External Program Memory Read Cycle t LHLL ALE t AVLL PSEN PORT 0 PORT 2 External Data Memory Read Cycle t LHLL ALE PSEN RD t AVLL PORT FROM RI OR DPL PORT 2 P2 A15 FROM DPH AT80F52 3-30 t LLIV t LLPL t PLIV t PLAZ t PXIZ t LLAX t PXIX INSTR IN t AVIV A8 - A15 ...
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External Data Memory Write Cycle t LHLL ALE PSEN WR t AVLL PORT FROM RI OR DPL PORT 2 P2 A15 FROM DPH External Clock Drive Waveforms t CHCX V - ...
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... V - 0. TEST POINTS 0 0.45V Note Inputs during testing are driven at V for a logic 1 and 0.45V for a logic 0. Timing mea- surements are made at V max. for a logic 0. AT80F52 3-32 = 5.0V 20% and Load Capacitance = 80 pF MHz Osc Min 1.0 700 ...
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... Wide, Plastic Dual Inline Package (PDIP) Ordering Code AT80F52-12AC AT80F52-12JC AT80F52-12PC AT80F52-12AI AT80F52-12JI AT80F52-12PI AT80F52-16AC AT80F52-16JC AT80F52-16PC AT80F52-16AI AT80F52-16JI AT80F52-16PI AT80F52-20AC AT80F52-20JC AT80F52-20PC AT80F52-20AI AT80F52-20JI AT80F52-20PI Package Type Package Operation Range 44A Commercial 44J ( 40P6 44A ...