m37702s1afp Mitsumi Electronics, Corp., m37702s1afp Datasheet - Page 32

• Manufacturer Part Number: m37702s1afp
• Description: Single-chip 16-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

Bit 6 is the parity bit selection bit which indicates whether to add
parity bit or not.
Bits 4 to 6 should be set or reset according to the data format of
the communicating devices.
Bit 7 is the sleep selection bit. The sleep mode is described later.
The UART
termine whether to use CTS
____
CTS
“1”.
If CTS
start transmission by external CTS
later.
Transmission
Transmission is started when the bit 0 (TE
receive control register 1 is “1”, the bit 1 (TI
input is “L” if CTS
data is output from the TxD
specified by the bits 4 to 6 of UART
ter. The data is output from the least significant bit.
The TIi flag indicates whether the transmission buffer is empty or
not. It is cleared to “0” when data is written in the transmission
buffer and set to “1” when the contents of the transmission buffer
register is transferred to the transmission register.
Fig. 42 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit is selected.
32
____
i
f
RE
R
Receive
Clock
RI
RTS
i
input is used if bit 2 is “0” and RTS
or f
x
i
i
D
i
input is selected, the user can control whether to stop or
i
i
EXT
i
transmit/receive control register 0 bit 2 is used to de-
____
i
input is selected. As shown in Figure 40 and 41,
Starting at the falling
edge of start bit
____
i
i
input or RTS
Start bit
pin with the stop bit and parity bit
____
i
i
____
input. RTS
transmit/receive mode regis-
____
Check to be “L” level
i
i
i
output is used if bit 2 is
output.
flag) of UART
____
i
flag) is “0”, and CTS
i
will be described
M37702M2AXXXFP, M37702M2BXXXFP
i
transmit/
D
____
0
Get data
i
When the transmission register becomes empty after the contents
has been transmitted, data is transferred automatically form the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied.
Once transmission has started, the TE
nal (if CTS
completed.
Therefore, transmission does not stop until it completes even if the
TE
The transmission start condition indicated by TE
____
CTS
Therefore, data can be transmitted continuously if the next trans-
mission data is written in the transmission buffer register and TI
flag is cleared to 0 before the T
The bit 3 (TxEPTY
0 changes to “1” at the next cycle after the T
and changes to “0” when transmission starts. Therefore, this flag
can be used to determine whether data transmission is completed.
When the TI
in the UART
Receive
Receive is enabled when the bit 2 (RE
ceive control register 1 is set. As shown in Figure 42, the
frequency divider circuit at the receiving end begin to work when a
start bit is arrived and the data is received.
i
M37702S1AFP, M37702S1BFP
flag is cleared during transmission.
i
is checked while the T
____
D
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
i
input is selected) are ignored until data transmission is
i
i
transmission interrupt control register is set to “1”.
flag changes from “0” to “1”, the interrupt request bit
i
flag) of UART
D
7
MITSUBISHI MICROCOMPUTERS
ENDi
ENDi
signal shown in Figure 40 is “H”.
i
Stop bit
transmit/receive control register
signal goes “H”.
i
i
flag, TI
flag) of UART
ENDi
i
flag, and CTS
i
flag, TI
signal goes “H”
i
Start bit
transmit/re-
i
____
flag, and
i
sig-
i