pa7536 ETC-unknow, pa7536 Datasheet
pa7536
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pa7536 Summary of contents
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... Input registers/latches and 12 buried registers/latches). Its logic array implements 50 sum-of-products logic functions that share 64 product terms. The PA7536’s logic and I/O cells (LCCs, IOCs) are extremely flexible offering up to three output functions per cell (a total of 36 for all 12 logic cells) ...
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... I/CLK lobal Cells PA 7536 Logic Array Figure 3 PA7536 Logic Array True Product-Term Sharing The PEEL™ logic array provides several advantages over common PLD logic arrays. First, it allows for true product- term sharing, not simply product-term steering, as commonly found in other CPLDs. Product term sharing ensures that product-terms are used where they are needed and not left unutilized or duplicated ...
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Sum Sum-A Sum-B = Preset Sum-B Sum-C = Reset, Clock, Sum-C Sum-D = Clock, Output Enable, Sum after clocked Best ...
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... LCCs I/O I/O w ith independent output enable Figure 10. Global Cells 08-16-008A utput 08-16-009A Figure 11. Register Type Change Feature 4 The PA7536 provides two CLK1 CLK2 M UX PCLK Global C ell CLK1 CLK2 M UX PCLK Reg-Type Preset Reset G lobal C ell & ...
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... Figure 12, Figure 13 and Figure 14) Figure 12 - PLACE Architectural Editor for PA7536 PEEL™ Array development is also supported by popular development tools, such as ABEL and CUPL, via ICT’s PEEL™ Array fitters. A special smart translator utility adds ...
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Table 1. Absolute Maximum Ratings Symbol Parameter V Supply Voltage Voltage Applied to Any Pin Output Current O T Storage Temperature ST T Lead Temperature LT Table 2. Operating Ranges Symbol Parameter V ...
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Table 4. A.C Electrical Characteristics Combinatorial Symbol Propagation delay Internal (t t PDI Propagation delay External (t t PDX Input or I/O pin to array input t IA Array input to LCC t AL LCC input to LCC output t ...
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Table 5. A.C. Electrical Characteristics Sequential Symbol Internal set-up to system clock t SCI ( Input (EXT.) set-up to system clock, - LCC (t t SCX System-clock to ...
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Figure 16. Sequential Timing – Waveforms and Block Diagram Notes 1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V for periods less than 20ns. 2.Test points for Clock and ...
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... Table 6. Ordering Information Part Number PA7536P-15 PA7536J-15 PA7536S-15 PA7536PI-15 PA7536JI-15 PA7536SI-15 Figure 17. Part Number Package P = Plastic 600mil DIP S = SOIC J = Plastic (J) Leaded Chip Carrier (PLCC) Anachip USA, Inc. 780 Montague Expressway, #201 San Jose, CA 95131 TEL (408) 321-9600 FAX (408) 321-9696 ©2002 Anachip Corp. ...