bh25rb1wgut ROHM Co. Ltd., bh25rb1wgut Datasheet - Page 5

• Manufacturer Part Number: bh25rb1wgut
• Description: Ultra Small Package Cmos Ldo Regulators
• Manufacturer: ROHM Co. Ltd.

Block Diagram, Recommended Circuit Diagram, and Pin Assignment Diagram
Power Dissipation (Pd)
Input Output Capacitors
© 2009 ROHM Co., Ltd. All rights reserved.
BH□□RB1WGUT Series
Fig. 26 Capacitance vs Bias (Y5V)
www.rohm.com
120
100
80
60
40
20
0
VSTBY
1.
2.
It is recommended to insert bypass capacitors between input and GND pins, positioning them as close to the pins as
possible. These capacitors are used when the power supply impedance increases or when long wiring paths are used, so
they should be checked once the IC has been mounted. Ceramic capacitors generally have temperature and DC bias
characteristics. Use X5R or X7R ceramic capacitors, which offer good temperature and DC bias characteristics as well as
stable high voltages.
0
Typical ceramic capacitor characteristics
VIN
*Circuit design should allow a sufficient margin for the temperature range for PMAX < Pd.
10 V
torelance
Cin
Power dissipation (Pd)
Power dissipation calculations include output power dissipation characteristics and internal IC power consumption.
In the event that the IC is used in an environment where this power dissipation is exceeded, the attendant rise in
the junction temperature will trigger the thermal shutdown circuit, reducing the current capacity and otherwise
degrading the IC's design performance. Allow for sufficient margins so that this power dissipation is not exceeded
during IC operation.
Power dissipation/power dissipation reduction (Pd)
BH□□RB1WGUT
G ND
STBY
1
Calculating the maximum internal IC power consumption (P
VIN
DC bias Vdc (V)
B2
A1
A2
P
2
MAX
16 V torelance
R EF ERE NCE
VO LTAG E
= (V
O VER CU RRE NT
Fig. 25 VCSP60N1 Power Dissipation/Power Dissipation Reduction (Example)
50 V
torelance
P RO T ECT IO N
P RO TE CTIO N
3
TH ERM A L
C O NT RO L
BLO CK
Cin: 1.0 F
Co: 1.0 F
IN
Fig. 24
- V
4
OUT
)  I
OUT
(MAX.)
100
95
90
85
80
75
70
0.6
0.4
0.2
0
0
Fig.27 Capacitance vs Bias
0
B 1
VCSP60N1
VOUT
25
1
(X5R, X7R)
10 V
torelance
DC bias Vdc (V)
VOUT
Co
50
5/8
Ta[ ℃ ]
2
530 mW
16 V torelance
50 V torelance
75
3
MAX
100
V
V
I
Pin No.
OUT
IN
OUT
)
B2
B1
A1
A2
: Input voltage
125
4
(MAX): Output current
: Output voltage
Board: 7 mm  7 mm  0.8 mm
Material: Glass epoxy PCB
Symbol
STBY
V
GND
1PIN MARK
V
OUT
IN
Fig. 28 Capacitance vs Temperature
120
100
80
60
40
20
0
-25
TOP VIEW (Mark side)
A
B
Power supply input
Voltage output
Ground
Output voltage on/off control
(High: ON, Low: OFF)
(X5R, X7R, Y5V)
1
0
Y5V
Temp[ ℃ ]
Function
2
Technical Note
2009.09 - Rev.B
25
X7R
X5R
50
75