ak4390 ETC-unknow, ak4390 Datasheet
ak4390
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ak4390 Summary of contents
Page 1
... The AK4390 is a high performance stereo DAC capable of sampling up to 216kHz including a 32-bit digital filter. The modulator uses AKM's multi-bit architecture, delivering wide dynamic range while preserving linearity for improved THD+N performance. The AK4390 has fully differential switched-cap filter outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter ...
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... MCLK Divider CSN/SMUTE CCLK/DEM0 CDTI/DEM1 CAD0 CAD1/DIF0 MS1046-E-00 VSS3 PDN 8X Interpolator DATT Soft Mute Control Register PSN DZFL/DIF1 DIF2 Block Diagram - 2 - [AK4390] VSS4 AVDD VSS2 VDDL AOUTLP SCF AOUTLN VREFHL ΔΣ VREFLL Vref Modulator VREFLR VREFLL AOUTRP SCF AOUTRN VDDR ...
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... Ordering Guide −10 ∼ +70°C AK4390EF AKD4390 Evaluation Board for AK4390 ■ Pin Layout SMUTE/CSN TST1/CAD0 DEM0/CCLK DEM1/CDTI DIF0/CAD1 DIF1/DZFL DIF2 PSN TST2/DZFR AOUTRP AOUTRN VSS1 VDDR VREFHR VREFLR MS1046-E-00 30pin VSOP (0.65mm pitch AK4390 Top 7 View ...
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... Master Clock Input Connected to VSS1/2/3 Ground Digital Power Supply, 4.75 ∼ 5.25V Power-Down Mode When at “L”, the AK4390 is in power-down mode and is held in reset. The AK4390 should always be reset upon power-up. Audio Serial Data Clock in PCM Mode Audio Serial Data Input in PCM Mode ...
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... Serial Control Mode Classification Pin Name AOUTLP, AOUTLN Analog AOUTRP, AOUTRN DIF2 Digital DZFL, DZFR MS1046-E-00 Pin Name Setting Leave open. AOUTLP, AOUTLN AOUTRP, AOUTRN Leave open. SMUTE Connect to VSS4. Setting Leave open. Leave open. Connect to VSS4. Leave open [AK4390] 2009/01 ...
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... IIN VIND Ta Tstg Note 1) Symbol min AVDD 4.75 VDDL/R 4.75 DVDD 4.75 VREFHL/R AVDD-0.5 VREFLL/R VSS3 Δ VREF 3 min max −0.3 6.0 −0.3 6.0 −0.3 6.0 ±10 - −0.3 DVDD+0.3 −10 70 −65 150 typ max 5.0 5.25 5.0 5.25 5.0 5.25 - AVDD - - - AVDD [AK4390] Units °C °C Units 2009/01 ...
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... Figure min 5) 0dBFS −60dBFS 0dBFS −60dBFS 0dBFS −60dBFS −60dBFS (Note 6) 114 (Note 7) 114 110 (Note 8) ±2.65 (Note 9) (Note 10) 1 (Note 11 [AK4390] 15; unless otherwise specified.) typ max Units 24 Bits −103 93 −57 - −100 - −54 - −100 - −54 - −51 - 120 120 120 0.15 0 ppm/°C ± ...
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... PR SA 100 14 Symbol min 13 Symbol min 13) SB 105 14 [AK4390] typ max Units 20.0 kHz 22.05 - kHz kHz ±0.005 1/fs ±0 typ max Units 43.5 kHz 48.0 - kHz kHz ±0.005 1/fs ±0 typ max Units 87 ...
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... PR SA 100 14 Symbol min 13 Symbol min 13) SB 105 14 [AK4390] typ max Units 20.0 kHz 22.05 - kHz kHz ±0.005 1/fs ±0 typ max Units 43.5 kHz 48.0 - kHz kHz ±0.005 1/fs ±0 typ max Units 87 ...
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... Note 15. TST1/CAD0 and PSN pins have internal pull-up devices, nominally 100kΩ. Therefore, TST1/CAD0 and PSN pins are not included in this specification. MS1046-E-00 DC CHARACTERISTICS Symbol min VIH 2.4 VIL - VOH DVDD−0.5 VOL - (Note 15) Iin - - 10 - [AK4390] typ max Units - - 0.5 V ±10 μA - ...
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... CCLK “↑” to CSN “↑” Reset Timing PDN Pulse Width Note 16. When the frequency (1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs) is switched, the AK4390 should be reset by the PDN pin or RSTN bit. Note 17. BICK rising edge must not occur at the same time as LRCK edge. ...
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... LRCK BICK tBCKH LRCK tBLR BICK SDATA MS1046-E-00 1/fCLK tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs tBCK tBCKL Clock Timing tLRB tSDS tSDH Audio Interface Timing (PCM Mode [AK4390] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2009/01 ...
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... CCLK CDTI D3 PDN MS1046-E-00 tCCKL tCCKH tCDS tCDH C1 C0 R/W WRITE Command Input Timing D2 D1 WRITE Data Input Timing tPD Power Down & Reset Timing - 13 - [AK4390] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH D0 VIL VIL 2009/01 ...
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... RSTN bit. After exiting reset (PDN pin = “L” → “H”) at power-up etc., the AK4390 is in power-down mode until MCLK is supplied. The AK4390 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode, and the analog output is AVDD/2 (typ) ...
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... Don’t care Don’t care Figure 2. Mode 1/4 Timing - 15 - [AK4390] Table 4. In all formats the serial data BICK Figure ≥ 32fs Figure 1 ≥ 48fs Figure 2 ≥ 48fs Figure 3 (default) ≥ 48fs Figure 4 ≥ 48fs Figure 2 ≥ ...
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... Figure 6. Mode 7 Timing - Don’t care Rch Data Don’t care Rch Data Rch Data Don’t care Rch Data [AK4390 2009/01 ...
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... Output Volume Control The AK4390 includes channel independent digital output volume control (ATT) with 256 levels at 0.5dB steps including MUTE. The volume control is in front of the DAC, and it can attenuate the input data from 0dB to –127dB and mute. When changing output levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions ...
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... The DZF pin immediately returns to “L” if the input data are not zero after going “H”. ■ System Reset The AK4390 should be reset once by bringing the PDN pin = “L” upon power-up. The analog section exits power-down mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during 4/fs. ...
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... Power ON/OFF timing The AK4390 is placed in the power-down mode by bringing the PDN pin “L” and the registers are initialized. the analog outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin signal, the analog output should be muted externally if the click noise influences system application. ...
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... RESET by RSTN bit = “0” When the RSTN bit = “0”, the AK4390’s digital section is powered down, but the internal register values are not initialized. The analog outputs settle to AVDD/2 (typ) and the DZF pins for both channels go to “H”. Figure 9 shows the example of reset by RSTN bit ...
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... The AK4390 is automatically placed in reset state when MCLK or LRCK is stopped during normal operation and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4390 exits reset state and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. ...
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... When the state of the PSN pin is changed, the AK4390 should be reset by the PDN pin. The serial control interface is enabled by the PSN pin = “L”. In this mode, pin settings must be all “L”. Internal registers may be written to through3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits, CAD0/1), Read/Write (1-bit ...
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... MSB justified 00H Disable 01H Separated 01H Sharp roll-off filter 01H OFF 01H Normal Operation 01H PCM mode 02H 512fs 02H Stereo 02H “H” active 02H R channel 02H - 23 - [AK4390] Bit PCM DSD Ex DF I/F ATT7 EXDF Y - ESC - - DIF2 DZFE Y Y DZFM Y Y ...
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... When the PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default values. When the state of the PSN pin is changed, the AK4390 should be reset by the PDN pin. ■ Register Definitions ...
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... Disable (default) 1: Enable The zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are always “L”. MS1046-E- DZFE DZFM (Table DEM1 DEM0 [AK4390] D0 SMUTE 0 2009/01 ...
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... MS1046-E- ATT7 ATT6 ATT5 ATT4 ATT7 ATT6 ATT5 ATT4 DZFB ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 [AK4390 ATT0 ATT0 1 2009/01 ...
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... VSS1 VSS2 VDDL 13 VDDR 14 VREFHR VREFHL 15 VREFLR VREFLL shows the analog output circuit examples. The Digital 5. 0.1u 10u 0.1u 10u 22 21 Lch Lch LPF Mute 20 19 0.1u 10u 0.1u 10u Analog 5.0V + Electrolytic Capacitor Ceramic Capacitor [AK4390] DSP Lch Out 2009/01 ...
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... AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R should be connected with a 0.1µF ceramic capacitor. All signals, especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4390. 3. Analog Outputs The analog outputs are fully differential outputs at 2.8Vpp (typ, VREFHL/R − ...
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... Stage 2 182kHz 284kHz 0.637 +3.9dB -0.88dB 20kHz -0.025 -0.021 40kHz -0.106 -0.085 80kHz -0.517 -0.331 - 29 - 1.5k 1n +Vop Analog Out -Vop 1n +15 -15 0.1u 560 1.0n 100 620 620 1.0n NJM5534D + 10u 0.1u Stage Total - - - +3.02dB -0.046dB -0.191dB -0.848dB [AK4390] 10u + Lch 2009/01 ...
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... VSOP (Unit: mm) *9.7 ± 0.1 0 0.22 ± 0.1 0.12 M NOTE: Dimension "*" does not include mold flash. ■ Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate MS1046-E-00 PACKAGE 16 15 0.65 Detail A 0. [AK4390] 1.5MAX A +0.10 0.15 -0.05 2009/01 ...
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... Date (YY/MM/DD) Revision 09/01/09 00 MS1046-E-00 MARKING AK4390EF XXXXXXXXX XXXXXXXXX Date code identifier REVISION HISTORY Reason Page Contents First Edition - 31 - [AK4390] 2009/01 ...
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... AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS1046-E-00 IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK4390] in any safety, life support, or Note1) 2009/01 ...