ak4317 ETC-unknow, ak4317 Datasheet
ak4317
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ak4317 Summary of contents
Page 1
... LPF. A 1bit DAC can achieve monotonicity and low distortion with no adjustment and is superior to traditional R-2R ladder based DACs. In the AK4317, the loss of accuracy from clock jitter is also improved by using SCF techniques for on-chip post filter. Therefore, the AK4317 is suitable for the system like STB including PLL circuit ...
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... Power Supply Digital I/F level X'tal Oscillator DR Package 2. Pin Compatibility The following pin functions are changed from AK4311/A. But when X'tal oscillating circuit is not used possible to change AK4311/A to AK4317 without changing the board layout. Pin No. AK4311 0172-E-01 -40 +85 C 24pin VSOP(0.65mm pitch) ...
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... DVDD - Digital Power Supply 2 DVSS - Digital Ground Pin Power-Down Mode Pin When at "L", the AK4317 is in power-down mode and is held in reset. The AK4317 should always be reset upon power-up. 4 DIF0 I Digital Input Format Pin 5 MCLK I Master Clock Input Pin 6 DIF1 ...
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... Analog output voltage scales with the voltage of VREF. AOUT(typ.@0dB)=2.8Vpp*VREF/5. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 0172-E-01 ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD VDA IIN VIND Ta Tstg Symbol min AVDD 4.5 DVDD 4.5 VREF 2 [AK4317] min max Units -0.3 6.0 V -0 ±10 mA -0.3 AVDD+0 ...
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... PSR is applied to AVDD,DVDD with 1kHz, 100mVpp. VREF pin is held +5V. 0172-E-01 ANALOG CHARACTERISTICS 10k ; unless otherwise specified) L min typ 18 -80 - 0.15 20 2.66 2 [AK4317] max Units Bits 0 ppm/ C 2.94 Vpp 120 1997/5 ...
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... Notes: 11. DIF0,DIF1,DEM,TST1 pins have internal pull-down devices, nominally 160k . 0172-E-01 FILTER CHARACTERISTICS Symbol min 22. DIGITAL CHARACTERISTICS Symbol min VIH 2.2 VIL - VOH DVDD-0.5 VOL - Iin - - 6 - [AK4317] typ max Units 20.0 kHz - kHz kHz dB ±0.06 dB 14 ±0.5 typ max Units - - 0.5 ...
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... CS Pulse Width Low CCLK to CS falling CS rising to CCLK Reset Timing PD Pulse Width (Note 13 ) Notes: 12. BICK rising edge must not occur at the same time as LRCK edge. 13. The AK4317 can be reset by bringing PD "L" to "H" only upon power up. 0172-E-01 SWITCHING CHARACTERISTICS =20pF) L Symbol min fCLK 2 ...
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... ASAHI KASEI Timing Diagram PD 0172-E-01 tPD VIL Reset Timing - 8 - [AK4317] 1997/5 ...
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... If these clocks are not provided, the AK4317 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4317 should be in the power-down mode(PD="L"). After exiting reset at power-up etc., the AK4317 is in power- down mode until MCLK and LRCK are input. ...
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... ASAHI KASEI De-emphasis filter The AK4317 includes the digital de-emphasis filter(tc=50/15us) by IIR filter. This filter corresponds to three sampling frequencies(32kHz,44.1kHz,48kHz). De-emphasis is enabled by the following two ways. 1. DEM pin Only one de-emphasis(fs=44.1kHz) set initially can be controlled by DEM pin at resetting. The de- emphasis is enabled by setting DEM pin " ...
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... As the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF goes to "H". DZF immediately go to "L" if input data are not zero after DZF "H". Figure 5 . Soft mute and zero detection 0172-E- [AK4317] 1997/5 ...
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... Note 1: CCLK should be held "H" or "L" except writing to ATT & mode registers in order to avoid the performance degradation. Note 2: If the above serial mode control is not used, CS should be held "H". 1. Attenuator Operation The AK4317 has individually controllable attenuator with linear scale and 256 levels for each channel. Equation of attenuation level: ATT=20×Log FFH: 0dB : 01H: -48 ...
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... ASAHI KASEI 2. Output mode The AK4317 supports the following output modes. Normal stereo output L/R Reverse output Monaural output: L/L, R/R, (L+R)/2 Output muting with soft mute operation When resetting, ATT values of both channels are FFH and the attenuation levels are set 0dB. The output mode is also set normal stereo output ...
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... ASAHI KASEI Power-Down The AK4317 are placed in the power-down mode by bringing PD pin "L" and the analog outputs are floating(Hi-Z). Figure 8 shows an example of the system timing at the power-down and power-up. Figure 8 . Power-down/up sequence example Notes: Analog output corresponding to digital input have the group delay(GD). ...
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... When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - The capacitor value on VCOM depends on low frequency noise level of power supply. - All input pins except pull-down pins(DIF0,DIF1,DEM,TST1) should not be left floating. 0172-E-01 SYSTEM DESIGN - 15 - [AK4317] 1997/5 ...
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... The output voltage is a positive full scale for 1FFFFH(@18bit) and a negative full scale for 20000H(@18bit). The ideal output is VCOM voltage for 00000H(@18bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV. 0172-E- [AK4317] 1997/5 ...
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... ASAHI KASEI 24pin VSOP (Unit: mm) NOTE: Dimension “*” does not include mold flash. Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: 0172-E-01 PACKAGE Epoxy Cu Solder plate - 17 - [AK4317] 1997/5 ...
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... ASAHI KASEI 0172-E-01 MARKING Contents of AAXXXX AA: Lot# XXXX: Date Code - 18 - [AK4317] 1997/5 ...
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IMPORTANT NOTICE These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability ...