pt7a4402b Pericom Technology Inc, pt7a4402b Datasheet

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pt7a4402b

Manufacturer Part Number
pt7a4402b
Description
T1/e1 System Synchronizer
Manufacturer
Pericom Technology Inc
Datasheet

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PT0100(12/05)
Features
• Supports AT&T TR62411 Stratum 3, 4 and
Applications
• Synchronization and timing control for multitrunk
Stratum 4 Enhanced for DS1 interfaces and for
ETSI ETS 300 011, TBR 4, TBR 12, and TBR
13 for E1 interfaces
Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
Provides three kinds of 8kHz ST-BUS framing
signals
Two independent reference inputs
Input reference frequency 1.544MHz, 2.048MHz
or 8kHz selectable
Provides bit error free reference switching and
meets phase slope and MTIE requirements
Normal, Holdover or Free-Run operating modes
available
Automatic reference input impairment monitor
Power supply: 5V (4402B) and 3.3V(4402L)
T1 and E1 systems
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
1
Description
PT7A4402B/4402L employs a digital phase-locked loop
(DPLL) to provide timing and synchronizing signals for
multitrunk T1 and E1 primary rate transmission links. The
ST-BUS clock and framing signals are phase-locked to
input reference signals of either 2.048 MHz, 1.544MHz
or 8 kHz.
The PT7A4402B/4402L meets the requirements for
AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced,
and ETSI ETS 300 011 in jitter tolerance, jitter transfer,
intrinsic jitter, frequency accuracy, holdover accuracy,
capture range, phase slope and MTIE, etc.
The PT7A4402B/4402L operates in Manual or Automatic
Mode, and in each of the modes, three operating states
are available: Normal, Holdover and Free-Run.
Ordering Information
P
P
a P
a P
a P
a P
a P
P
P
T
T
T
T
7
7
t r
t r
t r
t r
t r
7
7
A
A
A
A
N
N
N
N
N
4 4
4 4
4 4
4 4
u
u
u
u
u
2 0
2 0
m
m
m
m
m
2 0
2 0
T1/E1 System Synchronizer
b
b
b
b
b
B
L
J B
J L
r e
r e
r e
r e
r e
E J
E J
PT7A4402B/4402L
e L
e L
d a
d a
8 2
8 2
r f
r f
e e
e e
P
P
P
P
P
P -
P -
Data Sheet
c a
c a
c a
c a
c a
n i
n i
8 2
8 2
a k
a k
a k
a k
a k
P
P
P -
P -
e g
e g
e g
e g
e g
L
L
n i
n i
C
C
C
C
P
P
L
L
C
C
C
C
Ver:1

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pt7a4402b Summary of contents

Page 1

... ETSI ETS 300 011 in jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, holdover accuracy, capture range, phase slope and MTIE, etc. The PT7A4402B/4402L operates in Manual or Automatic Mode, and in each of the modes, three operating states are available: Normal, Holdover and Free-Run. ...

Page 2

... Functional Description .................................................................................................................................. 7 Overall Operation .................................................................................................................................. 7 Modes and States of Operation ............................................................................................................ 10 Applications Information....................................................................................................................... 14 Detailed Specifications ................................................................................................................................ 16 Definitions of Critical Performance Specifications .................................................................................. 16 Absolute Maximum Ratings .................................................................................................................. 18 Recommended Operating Conditions.................................................................................................... 18 DC Electrical and Power Supply Characteristics ................................................................................... 19 AC Electrical Characteristics ................................................................................................................ 20 Mechanical Specifications ........................................................................................................................... 33 Note .......................................................................................................................................................... 34 PT0100(12/05) T1/E1 System Synchronizer Contents 2 Data Sheet PT7A4402B/4402L Ver:1 ...

Page 3

... LOS2 MS1 PT0100(12/05) T1/E1 System Synchronizer V GND TCLR CC Virtual Reference TIE DPLL Corrector State State Select Select Input Impairment Monitor Guard Time Circuit MS2 GTo GTi 3 Data Sheet PT7A4402B/4402L C1.5 C2 Output C3 Interface C4 Circuit C8 C16 F0 F8 F16 Feedback Frequency Select MUX FS1 FS2 Ver:1 ...

Page 4

... RSEL 6 24 MS1 7 23 MS2 8 28-Pin PLCC 22 LOS1 9 21 LOS2 10 20 GTo 11 19 GTi Top View 4 Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 5

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 6

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 7

... Referring to the block diagram on Page 3, the detailed functions of the PT7A4402B/4402L are described as follows. Master Clock The PT7A4402B/4402L uses either an external clock source or an external crystal and a few discrete components with its inter- nal oscillator as the master clock. Reference Select MUX The PT7A4402B/4402L accepts two independent reference sig- nals, the primary reference and secondary reference ...

Page 8

... DCO will generate the corresponding digital output signals for the Tapped Delay Line in the Output Interface Cir- cuit to produce 12.352MHz and 16.384MHz signals. The DCO synchronization method depends upon the PT7A4402B/4402L operating state, as follows: In Normal state, the DCO generates an output signal which is frequency and phase locked to the selected input reference signal ...

Page 9

... Filter Control Circuit State Select From State Select Input Impairment From Monitor State Machine T1 Tapped 12MHz Divider Delay Line Tapped E1 16MHz Delay Divider Line 9 Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer DPLL Reference to DCO Output Interface Circuit C1 C16 F0 F8 F16 Ver:1 ...

Page 10

... PT0100(12/05) PT7A4402B/4402L T1/E1 System Synchronizer Modes and States of Operation The PT7A4402B/4402L operates either in Manual mode or Au- tomatic mode. Each mode has three possible operating states, Normal, Holdover or Free-Run. Shown in Table 4 and Table 5 are the mode and state selection instructions, using pins MS1, MS2, and RSEL. ...

Page 11

... Typically he Free-Run State is used when a master clock is required or immediately following system power-up before net- work synchronization is achieved. In Free-Run State, the outputs of the PT7A4402B/4402L are uncorrelated with the input reference signal and the stored in- formation of output reference. Instead, these output signals are based solely on the master clock frequency (OSCi) ...

Page 12

... S1A Auto-Holdover Secondary Primary (001) (000) S2H S1H Holdover Holdover Secondary Primary (011) (010) * Movement to Normal State from any state requires a valid input signal. 12 Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 13

... Primary Secondary (X0X) (011) (X0X) (011) (010 or 11X) S2H S1H Holdover Holdover Secondary Primary * Movement to Normal State from any state requires a valid input signal. 13 Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 14

... If the PRI signal returns to nor- mal before the expiration of the guard time (level at GTi pin is low), the PT7A4402B/4402L will return to Normal State with PRI input reference. If the PRI signal is still degraded after expira- tion of the guard time (level at GTi becomes high), the reference switching (from PRI to SEC) will occur ...

Page 15

... Figure 11. Unsymmetrical Guard Time Circuit PT7A4402B/4402L GTo + C 10µF GTi Good Bad Good Bad PRI PRI PRI Holdover Normal Holdover 15 Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer R C 150kΩ 10µ 1kΩ 1kΩ Good SEC PRI Normal Normal Ver:1 ...

Page 16

... AC Electrical Characteristics; as the remaining combinations can be derived from them. For the PT7A4402B/4402L, two internal elements determine the jitter attenuation. They are internal 1.9Hz low pass loop filter and phase slope limiter. The phase slope limiter limits the out- put phase slope to 5ns/125µ ...

Page 17

... Capture Range can fall outside the Lock Range, and, in general, the Capture Range is more narrow than the Lock Range. However, owing to the design of its Phase Detector, the PT7A4402B/ 4402L`s Capture Range is equal to its Lock Range. Phase Slope: Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal of constant frequency ...

Page 18

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 19

... and V measurement Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 20

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer * ...

Page 21

... Timing Reference Points 21 Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 22

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 23

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 24

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 25

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 26

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 27

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 28

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 29

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 30

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 31

... Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer ...

Page 32

... For Free-Run State of ±100ppm. 18. For capture range of ±230ppm. 19. For capture range of ±198ppm. 20. For capture range of ±130ppm. 21. 25pF capacitive load. PT0100(12/05) PT7A4402B/4402L T1/E1 System Synchronizer 22. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI p-p where 1UI p-p = 1/20MHz. 23. Jitter on reference input is less than 7ns p-p. 24. Applied jitter is sinusoidal. ...

Page 33

... Mechanical Specifications Figure 19. 28-pin PLCC PT0100(12/05) PT7A4402B/4402L T1/E1 System Synchronizer 33 Data Sheet ...

Page 34

... Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0100(12/05) Note Pericom Technology Inc. Web-Site: www.pti.com.cn, www.pti-ic.com Fax: (86)-21-6485 2181 Fax: (852)- 2243 3667 Fax: (1)-408-435 1100 34 Data Sheet PT7A4402B/4402L T1/E1 System Synchronizer Ver:1 ...

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