xwm8722eds ETC-unknow, xwm8722eds Datasheet - Page 18

• Manufacturer Part Number: xwm8722eds
• Description: Stereo Dac With Integrated Tone Generator And Line/variable Level Outputs
• Manufacturer: ETC-unknow

WM8722
Table 9 Programmable Output Format
REGISTER 3
REGISTER 4/5
PL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PL1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PL2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DAC OUTPUT CONTROL
Bits 5, 6, 7 and 8 (PL[3:0]) of register 2 are used to control the output format.
AUDIO DATA INPUT FORMAT
WM8722 allows maximum flexibility over the control of the audio data interface, allowing selection of
format type, word length, and sample rates.
DIGITAL AUDIO SERIAL PROTOCOL
A low on bit 0 sets the format to Normal (MSB-first, right justified format), whilst a high sets the
format to I
AUDIO INTERFACE CLOCKS
Bit 1 (LRP) of register 3 is used to control the polarity of LRCIN (sample rate clock). When bit 1 is
low, left channel data is assumed when LRCIN is in a high phase and right channel data is assumed
when LRCIN is in a low phase. When bit 1 is high, the polarity assumption is reversed.
ATTENUATOR CONTROL
Bit 2 in register 3 (A1[1:0] = 11) is used to control the attenuator (ATC). When ATC is high, the
attenuation data loaded in program register 0 is used for both the left and the right channels. When
ATC is low, the attenuation data for each register is applied separately to left and right channels.
ANALOGUE MIXER TRIM
Bits 0-4 of register 4, MTRIML[0:4], set the gain level of the first stage of analogue mixing on the left
channel. The 5-bit register selects 1.5 dB increments of the MIXINL signal, over a range of +12dB to
–34.5dB. A 6
Similarly, bits 0-4 of register 5, MTRIMR[0:4], set the attenuation level of the first stage of analogue
mixing on the right channel. The 5-bit register allows 1.5 dB increments of the MIXINR signal, over a
range of +12dB to –34.5dB. A 6
2
PL3
S (Philips serial data protocol).
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
th
bit, MUTE, controls muting of the signal when set high.
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
LEFT OUTPUT
th
bit, MUTE, controls muting of the signal when set high.
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
RIGHT OUTPUT
Mute Both Channels
Reverse Channels
Stereo Mode
Mono Mode
NOTE
AI Rev 2.1 June 2001
Advanced Information
18