pex8617 PLX, pex8617 Datasheet

pex8617

Manufacturer Part Number

pex8617

Description

Pcie Gen 2, 5.0gt/s 16-lane, 4-port Switch

Manufacturer

PLX

Datasheet

1.PEX8617.pdf (4 pages)

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Features

o 16-lane, 4-port PCIe Gen 2 switch

o 19 x 19mm

o Typical Power: 1.93 Watts

o Standards Compliant

o High Performance

o Flexible Configuration

o Dual-Host & Fail-Over Support

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

PEX 8617 General Features

PEX 8617 Key Features

- Integrated 5.0 GT/s SerDes

- PCI Express Base Specification, r2.0

- PCI Power Management Spec, r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Dynamic SerDes speed control

- Non-blocking switch fabric

- Full line rate on all ports

- Packet Cut-Thru with 140ns max packet

- 2KB Max Payload Size

- Read Pacing (bandwidth throttling)

- Dual Cast

- Ports configurable as x1, x2, x4, x8

- Registers configurable with strapping

- Lane and polarity reversal

- Compatible with PCIe 1.0a PM

- Configurable Non-Transparent port

- Moveable upstream port

- Crosslink port capability

- SSC Isolation

- Two Virtual Channels

- Eight traffic classes per port

- Weighted round-robin source

- 2 Hot-Plug Ports with native HP Signals

- All ports Hot-Plug capable thru I

- ECRC and Poison bit support

- Data Path parity

- Memory (RAM) Error Correction

- INTA# and FATAL_ERR# signals

- Advanced Error Reporting

- Port Status bits and GPIO available

- Per port error diagnostics

- Performance Monitoring

- JTAG AC/DC boundary scan

(backwards compatible w/ PCIe r1.0a/1.1)

latency (x4 to x4)

pins, EEPROM, I

port arbitration

(Hot-Plug Controller on every port)

• Per port payload & header counters

Version 1.1 2009

, 324-pin PBGA package

C, or host software

The ExpressLane

capability enabling users to add scalable high bandwidth, non-blocking

interconnection to a wide variety of applications including

workstations, storage systems, communications platforms,

embedded systems, and intelligent I/O modules. The PEX 8617 is

well suited for fan-out, aggregation, and peer-to-peer applications.

High Performance & Low Packet Latency

The PEX 8617 architecture supports packet cut-thru with a maximum

latency of 140ns (x4 to x4). This, combined with large packet memory and

non-blocking internal switch architecture, provides full line rate on all ports

for performance-hungry applications such as servers and switch fabrics.

The low latency enables applications to achieve high throughput and

performance. In addition to low latency, the device supports a max payload

size of 2048 bytes, enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8617 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction as packets

pass through the switch.

Flexible Register & Port Configuration

The PEX 8617’s 4 ports can be configured to lane widths of x1, x2, x4, or

x8. Flexible buffer allocation, along with the device's flexible packet flow

control, maximizes throughput for applications where more traffic flows in

the downstream, rather than upstream, direction. Any port can be designated

as the upstream port, which can be changed dynamically. The PEX 8617 also

provides several ways to

configure its registers.

The device can be

configured through

strapping pins, I

interface, host software,

or an optional serial

EEPROM. This allows

for easy debug during

the development phase,

performance monitoring

during the operation

phase, and driver or

software upgrade.

Figure 1 shows some of

the PEX 8617’s

common port

configurations.

PCIe Gen 2, 5.0GT/s 16-lane, 4-port Switch

PEX 8617

PEX 8617 device offers PCI Express switching

Figure 1. Common Port Configurations

PEX 8617

x4 x4

x2 x2

PEX 8617

Related parts for pex8617

pex8617 Summary of contents

Page 1

... Data Integrity The PEX 8617 provides end-to-end CRC (ECRC) protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory (RAM) error correction as packets pass through the switch. ...

Page 2

... The PEX 8617 supports software control of the SerDes outputs to allow optimization of power and signal Secondary Host strength in a system. The PLX SerDes implementation CPU supports four levels of power – off, low, typical, and high. The SerDes block also supports loop-back modes and advanced reporting of error conditions, which enables efficient management of the entire system ...

Page 3

CPU CPU CPU CPU Chipset x16 Endpoint x16 PEX 8617 x4 Endpoint x4 PCIe Gen1 or PCIe Gen2 slots Figure 3. Fan-in/out Usage Network Interface Cards The PEX 8617 can also be utilized in communications applications such as Network Interface ...

Page 4

... PEX 8617. For more information, please refer to the PEX 8617RDK Product Brief. Part Number Description PEX8617-BA50BC 16-Lane, 4-Port PCI Express Switch (19x19mm PEX8617-BA50BC G 16-Lane, 4-Port PCI Express Switch, Pb-Free (19x19mm PEX8617BA-AIC4U4D RDK PEX 8617 Rapid Development Kit http://www.plxtech.com 2 ) for sampling ...

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