pex8609 PLX, pex8609 Datasheet

pex8609

Manufacturer Part Number

pex8609

Description

8 Lane, 8 Port Pci Express Switch, 15 X 15mm Pbga

Manufacturer

PLX

Datasheet

1.PEX8609.pdf (4 pages)

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Features

PEX 8609 General Features

o 8-lane PCI Express switch

o Up to 8 configurable ports

o 15 x 15mm

o Typical Power: 1.2 Watts

PEX 8609 Key Features

o Standards Compliant

o Integrated DMA Engine

o Dual-Host & Fail-Over Support

o High Performance

o Flexible Configuration

o PCI Express Power Management

o Spread Spectrum Clock Isolation

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

- Integrated 5.0 GT/s SerDes

- PCI Express Base Specification r2.0

- PCI Power Management Spec r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Four DMA Channels

- Internal Descriptor Support

- DMA function independent from

- 64-bit Addressing

- Prefetch Descriptor Mode

- Up to 4.0 GB/s throughput per channel

- Configurable Non-Transparent port

- Moveable upstream port

- Crosslink port capability

- Cut-Thru latency: 140ns

- 2KB max payload size

- Read Pacing

- Dual-Cast

- 8 flexible & configurable ports

- Configurable with strapping pins,

- Lane and polarity reversal

- Link power management states: L0, L0s,

- Device states: D0 and D3

- Dual clock domain

- Two Virtual Channels (VC) per port

- Eight Traffic Classes per port

- Weighted Round-Robin Port & VC

- All ports Hot-Plug capable thru I

- Data path protection

- Memory (RAM) error correction

- Port Status bits and GPIO available

- Per port error diagnostics

- Performance monitoring

(Backwards compatible with PCIe

r1.0a/1.1)

transparent switch function

(NTB)

(x1 or x4)

EEPROM, I

L1, L2/L3 Ready, and L3

Arbitration

(Hot-Plug Controller on every port)

(per port payload & header counters)

Version 1.0 2008

, 196-ball PBGA

C, or Host software

Preliminary Information Subject to Change – PLX Confidential

hot

The ExpressLane

enabling users to add scalable high bandwidth non-blocking interconnection to a

wide variety of applications including control planes, communication platforms,

servers, storage systems and embedded systems. The PEX 8609 is well suited for

fan-out, aggregation, peer-to-peer, and intelligent I/O module applications

Low Packet Latency & High Performance

The PEX 8609 architecture supports packet cut-thru with a maximum latency of

140ns. This, combined with large packet memory and non-blocking internal switch

architecture, provides full line rate on all ports for low-latency applications such as

communications and servers. The low latency enables applications to achieve high

throughput and performance. In addition to low latency, the device supports a max

payload size of 2048 bytes, enabling the user to achieve even higher throughout

Integrated DMA Engine

The PEX 8609 provides a versatile and powerful DMA engine built in to the device

which can be used as a stand alone DMA engine. The DMA engine removes the

burden resulting from having to move data between devices away from the

processor. This allows the processor to perform computational tasks instead. The

four DMA channels can support high data rate transfers between IO devices

connected to any of the available ports in the PEX8609. Additionally, the DMA

engine in the PEX 8609 can be used to complement the DMA engine in the

processor by providing additional DMA channels for higher performance.

Data Integrity

The PEX 8609 provides end-to-end CRC protection (ECRC) and Poison bit support

to enable designs that require guaranteed error-free packets. PLX also supports

data path parity and memory (RAM) error correction as packets pass through the

switch

Dual-Host and Fail-Over Support

The PEX 8609 supports full non-transparent bridging (NTB) functionality to allow

implementation of multi-host systems and intelligent I/O modules in applications

which require redundancy support such as communications, storage, and servers.

Non-transparent bridges allow systems to isolate host memory domains by

presenting the processor subsystem as an endpoint rather than another memory

system. Base address registers are used to translate addresses; doorbell registers are

used to send interrupts between the address domains; and scratchpad registers are

accessible from both address domains to allow inter-processor communication

Interoperability

The PEX 8609 is designed to be fully compliant with the PCI Express Base

Specification r2.0 and is backwards compatible to PCI Express Base Specification

r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and

polarity reversal. Furthermore, the PEX 8609 is designed for Microsoft Vista

compliance. All PLX switches undergo thorough interoperability testing in PLX’s

Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure

compatibility with PCI Express devices in the market.

Flexible & Versatile 8-lane 8-port PCI Express

PEX 8609

™

PEX 8609 device offers PCI Express switching capability

Switch

Related parts for pex8609

pex8609 Summary of contents

Page 1

... This allows the processor to perform computational tasks instead. The four DMA channels can support high data rate transfers between IO devices connected to any of the available ports in the PEX8609. Additionally, the DMA engine in the PEX 8609 can be used to complement the DMA engine in the processor by providing additional DMA channels for higher performance ...

Page 2

... PCI slots or Generic devices through the use of the PEX 8311 and PEX 8112 PCIe bridging devices. The DMA engine in the PEX8609 can alternatively be used for data transfers between the ASICs, FPGAs and the host. The integrated DMA engine together with the PEX8609 ...

Page 3

... In this case, there is an Active host and a Standby host ready to take over the system in the event the Active host fails. The DMA engine in the PEX8609 can be used to mirror the data between hosts thus minimizing the failover time. Generic Data Mover The DMA engine in the PEX8609 is very flexible ...

Page 4

... BIOS or host can configure the other ports using standard PCI enumeration. The DMA function of the PEX8609 implements a Type 0 header, same as an endpoint, and requires a driver. The driver for the DMA function is available from PLX and included in the SDK. ...

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