pex8648 PLX, pex8648 Datasheet

pex8648

Manufacturer Part Number

pex8648

Description

Pcie Gen2, 5.0gt/s 48-l Ne, 12-port Pcie Switch A

Manufacturer

PLX

Datasheet

1.PEX8648.pdf (4 pages)

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Download datasheet (248Kb)

Features

o 48-lane, 12-port PCIe Gen2 switch

o 27 x 27mm

o Typical Power: 3.7 Watts

o Standards Compliant

o High Performance

o Flexible Configuration

o Dual-Host & Fail-Over Support

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

PEX 8648 Vitals

PEX 8648 Key Features

- Integrated 5.0 GT/s SerDes

- PCI Express Base Specification, r2.0

- PCI Power Management Spec, r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Dynamic SerDes speed control

- Non-blocking switch fabric

- Full line rate on all ports

- Packet Cut-Thru with 140ns max packet

- 2KB Max Payload Size

- Read Pacing (bandwidth throttling)

- Dual-Cast

- Ports configurable as x1, x2, x4, x8, x16

- Registers configurable with strapping

- Lane and polarity reversal

- Compatible with PCIe 1.0a PM

- Configurable Non-Transparent port

- Moveable upstream port

- Crosslink port capability

- Eight traffic classes per port

- Weighted round-robin source

- 3 Hot Plug Ports with native HP Signals

- All ports hot plug capable thru I

- ECRC and Poison bit support

- Data Path parity

- Memory (RAM) Error Correction

- INTA# and FATAL_ERR# signals

- Advanced Error Reporting

- Port Status bits and GPIO available

- Per port error diagnostics

- Performance Monitoring

(backwards compatible w/ PCIe r1.0a/1.1)

latency (x16 to x16)

pins, EEPROM, I

port arbitration

(Hot Plug Controller on every port)

• Per port payload & header counters

Version 1.0 2009

, 676-pin FCBGA package

C, or host software

The ExpressLane

capability enabling users to add scalable high bandwidth, non-blocking

interconnection to a wide variety of applications including servers,

storage systems, and communications platforms. The PEX 8648 is

well suited for fan-out, aggregation, and peer-to-peer applications.

High Performance & Low Packet Latency

The PEX 8648 architecture supports packet cut-thru with a maximum

latency of 140ns (x16 to x16). This, combined with large packet memory

and non-blocking internal switch architecture, provides full line rate on all

ports for performance-hungry applications such as servers and switch

fabrics. The low latency enables applications to achieve high throughput and

performance. In addition to low latency, the device supports a packet payload

size of up to 2048 bytes, enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8648 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction as packets

pass through the switch.

Flexible Register & Port Configuration

The PEX 8648’s 12 ports can be configured to lane widths of x1, x2, x4, x8,

or x16. Flexible buffer allocation, along with the device's flexible packet

flow control, maximizes throughput for applications where more traffic

flows in the downstream, rather than upstream, direction. Any port can be

designated as the upstream port, which can be changed dynamically. The

PEX 8648 also provides

several ways to

configure its registers.

The device can be

configured through

strapping pins, I

interface, host

software, or an optional

serial EEPROM. This

allows for easy debug

during the development

phase, performance

monitoring during the

operation phase, and

driver or software

upgrade. Figure 1

shows some of the PEX

8648’s common port

configurations.

PCIe Gen2, 5.0GT/s 48-l ne, 12-port PCIe Switch

PEX 8648

PEX 8648 device offers PCI Express switching

Figure 1. Common Port Configurations

PEX 8648

11 x4

10 x4

2 x8

4 x8

PEX 8648

6x4

2 x4

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