pex8632 PLX, pex8632 Datasheet

pex8632

Manufacturer Part Number

pex8632

Description

Pcie Gen2, 5.0gt/s 32-lane, 12-port Switch Technology

Manufacturer

PLX

Datasheet

1.PEX8632.pdf (4 pages)

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Features

o 32-lane, 12-port PCIe Gen2 switch

o 27 x 27mm

o Typical Power: < 5.5 Watts

o Standards Compliant

o High Performance

o Flexible Configuration

o Dual-Host & Fail-Over Support

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

PEX 8632 General Features

PEX 8632 Key Features

- Integrated 5.0 GT/s SerDes

- PCI Express Base Specification, r2.0

- PCI Power Management Spec, r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Dynamic SerDes speed control

- Non-blocking switch fabric

- Full line rate on all ports

- Packet Cut-Thru with 145ns max packet

- 2KB Max Payload Size

- Read Pacing (bandwidth throttling)

- Dual-Cast

- Ports configurable as x1, x2, x4, x8, x16

- Registers configurable with strapping

- Lane and polarity reversal

- Compatible with PCIe 1.0a PM

- Configurable Non-Transparent port

- Moveable upstream port

- Crosslink port capability

- Eight traffic classes per port

- Weighted round-robin source

- 3 Hot Plug Ports with native HP Signals

- All ports hot plug capable thru I

- ECRC and Poison bit support

- Data Path parity

- Memory (RAM) Error Correction

- INTA# and FATAL_ERR# signals

- Advanced Error Reporting

- Port Status bits and GPIO available

- Per port error diagnostics

- Performance Monitoring

- JTAG AC/DC boundary scan

(backwards compatible w/ PCIe r1.0a/1.1)

latency (x8 to x8)

pins, EEPROM, I

port arbitration

(Hot Plug Controller on every port)

N Per port payload & header counters

Version 0.8 2007

, 676-pin FCBGA package

C, or host software

x x x x x x x x

Preliminary - PLX Confidential

The ExpressLane

capability enabling users to add scalable high bandwidth, non-blocking

interconnection to a wide variety of applications including servers,

storage systems, and communications platforms. The PEX 8632 is

well suited for fan-out, aggregation, and peer-to-peer applications.

High Performance & Low Packet Latency

The PEX 8632 architecture supports packet cut-thru with a maximum

latency of 145ns (x8 to x8). This, combined with large packet memory and

non-blocking internal switch architecture, provides full line rate on all ports

for performance-hungry applications such as servers and switch fabrics.

The low latency enables applications to achieve high throughput and

performance. In addition to low latency, the device supports a max payload

size of 2048 bytes, enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8632 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction as packets

pass through the switch.

Flexible Register & Port Configuration

The PEX 8632’s 12 ports can be configured to lane widths of x1, x2, x4, x8,

or x16. Flexible buffer allocation, along with the device's flexible packet

flow control, maximizes throughput for applications where more traffic

flows in the downstream, rather than upstream, direction. Any port can be

designated as the upstream port, which can be changed dynamically. The

PEX 8632 also provides

several ways to configure

its registers. The device

can be configured

through strapping pins,

software, or an optional

serial EEPROM. This

allows for easy debug

during the development

phase, performance

monitoring during the

operation phase, and

driver or software

upgrade. Figure 1 shows

some of the PEX 8632’s

common port

configurations.

PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch

C interface, host

PEX 8632

PEX 8632 device offers PCI Express switching

Figure 1. Common Port Configurations

3 x4

PEX 8632

10 x2

8 x2

2 x8

PEX 8632

2 x4

x16

Related parts for pex8632

pex8632 Summary of contents

Page 1

... Data Integrity The PEX 8632 provides end-to-end CRC (ECRC) protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory (RAM) error correction as packets pass through the switch. ...

Page 2

... I SerDes Power and Signal Management The PEX 8632 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power – off, low, typical, and Secondary Secondary Secondary Secondary ...

Page 3

... PEX 8632’s NT port is used to isolate the backup system from the primary system. CPU CPU CPU CPU Chipset Chipset Chipset Chipset PEX 8632 PEX 8632 PEX 8632 PEX 8632 x8 Preliminary - PLX Confidential Fabric To Backplane CPU CPU CPU CPU CPU CPU CPU CPU Memory Memory Memory ...

Page 4

... RDK Product Brief. Product Ordering Information Part Number Description PEX8632-AA50BC G 32-Lane, 12-Port PCI Express Switch, Pb-Free (27x27mm PEX8632-AA RDK PEX 8632 Rapid Development Kit Please visit the PLX Web site at http://www.plxtech.com Preliminary - PLX Confidential or contact PLX sales at 408-774-9060 for sampling. ...

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