pex8624 PLX, pex8624 Datasheet
pex8624
Manufacturer Part Number
pex8624
Description
Pcie Gen2, 5.0gt/s 24-lane, 6-port Switch Technology
Manufacturer
PLX
Datasheet
1.PEX8624.pdf
(4 pages)
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Features
S
S
o 24-lane, 6-port PCIe Gen2 switch
o 19 x 19mm
o Typical Power: < 4.0 Watts
o Standards Compliant
o High Performance
o Flexible Configuration
o Dual-Host & Fail-Over Support
o Quality of Service (QoS)
o Reliability, Availability, Serviceability
PEX 8624 General Features
PEX 8624 Key Features
- Integrated 5.0 GT/s SerDes
- PCI Express Base Specification, r2.0
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 145ns max packet
- 2KB Max Payload Size
- Read Pacing (bandwidth throttling)
- Dual-Cast
- Ports configurable as x1, x2, x4, x8
- Registers configurable with strapping
- Lane and polarity reversal
- Compatible with PCIe 1.0a PM
- Configurable Non-Transparent port
- Moveable upstream port
- Crosslink port capability
- Eight traffic classes per port
- Weighted round-robin source
- 3 Hot Plug Ports with native HP Signals
- All ports hot plug capable thru I
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- INTA# and FATAL_ERR# signals
- Advanced Error Reporting
- Port Status bits and GPIO available
- Per port error diagnostics
- Performance Monitoring
- JTAG AC/DC boundary scan
(backwards compatible w/ PCIe r1.0a/1.1)
latency (x8 to x8)
pins, EEPROM, I
port arbitration
(Hot Plug Controller on every port)
N Per port payload & header counters
Version 0.8 2007
2
, 324-pin FCBGA package
2
C, or host software
2
C
x x x x x x x x
Preliminary - PLX Confidential
The ExpressLane
capability enabling users to add scalable high bandwidth, non-blocking
interconnection to a wide variety of applications including
workstations, storage systems, and communications platforms. The
PEX 8624 is well suited for fan-out, aggregation, and peer-to-peer
applications.
High Performance & Low Packet Latency
The PEX 8624 architecture supports packet cut-thru with a maximum
latency of 145ns (x8 to x8). This, combined with large packet memory and
non-blocking internal switch architecture, provides full line rate on all ports
for performance-hungry applications such as servers and switch fabrics.
The low latency enables applications to achieve high throughput and
performance. In addition to low latency, the device supports a max payload
size of 2048 bytes, enabling the user to achieve even higher throughput.
Data Integrity
The PEX 8624 provides end-to-end CRC (ECRC) protection and Poison bit
support to enable designs that require end-to-end data integrity. PLX also
supports data path parity and memory (RAM) error correction as packets
pass through the switch.
Flexible Register & Port Configuration
The PEX 8624’s 6 ports can be configured to lane widths of x1, x2, x4, or
x8. Flexible buffer allocation, along with the device's flexible packet flow
control, maximizes throughput for applications where more traffic flows in
the downstream, rather than upstream, direction. Any port can be designated
as the upstream port, which
can be changed dynamically.
The PEX 8624 also provides
several ways to configure its
registers. The device can be
configured through strapping
pins, I
software, or an optional
serial EEPROM. This allows
for easy debug during the
development phase,
performance monitoring
during the operation phase,
and driver or software
upgrade. Figure 1 shows
some of the PEX 8624’s
common port configurations.
PCIe Gen2, 5.0GT/s 24-lane, 6-port Switch
2
C interface, host
PEX 8624
TM
PEX 8624 device offers PCI Express switching
Figure 1. Common Port Configurations
x8
PEX 8624
PEX 8624
PEX 8624
PEX 8624
PEX 8624
PEX 8624
PEX 8624
PEX 8624
5 x4
x4 x4
x4
x8
x4
x8
PEX 8624
PEX 8624
PEX 8624
PEX 8624
PEX 8624
PEX 8624
PEX 8624
PEX 8624
x4 x4 x4
x8
x8
x8
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pex8624 Summary of contents
Page 1
... Data Integrity The PEX 8624 provides end-to-end CRC (ECRC) protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory (RAM) error correction as packets pass through the switch. ...
Page 2
... Host CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU strength in a system. The PLX SerDes implementation Blade Blade Blade Blade Blade Blade Blade Blade Blade Blade Blade Blade supports four levels of power – off, low, typical, and high ...
Page 3
... PEX 8624 PEX 8624 Chipset Chipset Chipset Chipset x8 PEX 8624 PEX 8624 PEX 8624 PEX 8624 x4 Figure 6. Dual Cast in Storage Systems Preliminary - PLX Confidential Switch Fabric I/O Blades NT PEX 8624 PEX 8624 PEX 8624 PEX 8624 Backplane Figure 5. Bladed Embedded System CPU CPU ...
Page 4
... RDK Product Brief. Product Ordering Information Part Number Description PEX8624-AA50BC G 24-Lane, 6-Port PCI Express Switch, Pb-Free (19x19mm PEX8624-AA RDK PEX 8624 Rapid Development Kit Please visit the PLX Web site at http://www.plxtech.com Preliminary - PLX Confidential or contact PLX sales at 408-774-9060 for sampling. ...