pex8114 ETC-unknow, pex8114 Datasheet
pex8114
Manufacturer Part Number
pex8114
Description
Expresslane ?ci Express-to-pci/pci-x Bridge
Manufacturer
ETC-unknow
Datasheet
1.PEX8114.pdf
(4 pages)
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Features
S
S
S
.
General Features
Scalable PCI Express Interface
Advanced PCI-X Interface
o Forward and Reverse bridging
o Reverse bridging root functions
o
o
o
o
o
o 1.0 V core supply voltage
o DC and AC JTAG (1149.1 and
o x4 Link (configurable as x1, x2 or x4)
o Full-duplex PCI Express lanes;
o Automatic lane reversal
o 8b/10b encoding
o Link training (auto-negotiate to
o 256 byte maximum payload size
o PCI Express Base specification 1.0a
o End-to-end CRC and data poisoning
o Advanced error reporting
o Link and device power management
o Advanced flow control
o Hot Plug
o Turn off unused lanes for power
o PCI-X (v 1.0b): 64 bits at 133, 100 or
o PCI 3.0: 32 or 64 bits at 66, 50, 33 or
o 8-outstanding split transactions
o Internal arbiter supports up to 4
o 3.3V I/O
o Message Signal Interrupt (MSI)
o Provides up to four PCI/PCI-X clocks
o Scratchpad and doorbell registers
Transparent and Non-transparent
bridging
Standard 256 Plastic BGA package
(17mm x 17mm)
Low power – 2W max.
No heat sink required
EEPROM configuration option
1149.6)
2.5 Gbps each
smallest link width)
compliant
reduction
66 MHz
25 MHz
external masters
support
Version 2.1 2004
x x x x x x x x x
x x x x x x x x x
Flexible, High-Performance Bridge in a Small Package
The PLX Technology ExpressLane PEX 8114 is a high performance bridge that
enables designers to migrate legacy PCI and PCI-X bus interfaces to the new
advanced serial PCI Express™ interface. This flexible device supports forward,
reverse and non-transparent bridging.
The bridge is equipped with a standard, but flexible PCI Express port that scales to
x1, x2 or x4 lanes with a maximum of 1 Gigabyte per second of throughput per
transmit and receive direction. With four 2.5 Gbps integrated SerDes, the standard
PCI Express signaling delivers the highest bandwidth with the lowest possible pin
count using LVDS technology.
The ExpressLane PEX 8114 has a single parallel bus segment supporting the
advanced PCI-X protocol, with a 64-bit wide parallel data path running at 133MHz.
The bridge also supports conventional PCI operation.
While both sides of the bridge are evenly matched, the device also supports internal
queues with flow control features to optimize throughput and traffic flow.
The small 17mm x 17mm footprint in standard Plastic BGA packaging makes the
ExpressLane PEX 8114 ideal for a variety of applications where board real estate is
at a premium.
Forward and Reverse Bridging
Compliant to the PCI Express-to-PCI/PCI-X Bridge Specification 1.0, the
ExpressLane PEX 8114 is capable of operating in either forward or reverse bridging
modes. In forward mode, the bridge allows legacy PCI or PCI-X chips and adapters
to be used with new PCI Express processor systems. Reverse bridge operation allows
conventional PCI or PCI-X processors and chipsets to configure and control
advanced PCI Express switches and endpoints. The reverse bridge not only allows
complete configuration of a downstream PCI Express system from the PCI/PCI-X
bus, but it also handles limited PCI Express root functions for reverse interrupt and
advanced error handling.
Non-Transparent Bridging
The ExpressLane PEX 8114 can be configured as a non-transparent bridge when
operating in forward mode. Non-transparent bridging is used to design intelligent I/O
and storage adapters as well as to enable multi-host systems. The non-transparency
features are implemented in the same fashion as conventional PCI-to-PCI bridge
applications.
Non-Transparent bridges allow systems to isolate CPU and memory spaces to
connect two independent address/processor domains. The bridge includes doorbell
registers to send interrupts from each side to the other and scratchpad registers
accessible from both sides for inter-processor communications.
High Performance PCI Express Interface
The fully integrated PCI Express interface incorporates many of the advanced
protocol features in PCI Express such as Automatic Lane Reversal, ECRC, Data
Poisoning, Link State Power Management and Hot Plug. The single link scales from
x4 to x2 or x1 operation through configuration or automatic link training. This
enables the user to reduce power consumption by turning off unused lanes.
ExpressLane™ PCI Express-to-PCI/PCI-X Bridge
PEX 8114
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pex8114 Summary of contents
Page 1
Version 2.1 2004 . Features S General Features o Forward and Reverse bridging o Reverse bridging root functions o Transparent and Non-transparent ...
Page 2
Board and System Design Applications The ExpressLane PEX 8114 can be used on PCI Express- based motherboards or embedded systems to connect with legacy PCI or PCI-X slots or devices. In addition, the bridge can be used in add-on cards ...
Page 3
Adapter Boards-Reverse Bridge The ExpressLane PEX 8114 supports Reverse Transparent Mode bridging (see Figure 5), enabling state-of-the-art PCI Express silicon to be used with legacy PCI or PCI-X parallel busses. Designers can utilize the latest LAN, SAN or NAS I/O ...
Page 4
Development Tools PLX offers hardware and software tools (PEX 8114RDK) to enable rapid customer design. These tools include the Hardware Development Kit (HDK) and the Software Development Kit (SDK). PEX 8114RDK The Forward Bridge RDK hardware module (Figure 8) includes ...