pex8716 PLX, pex8716 Datasheet

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pex8716

Manufacturer Part Number
pex8716
Description
Manufacturer
PLX
Datasheet

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Part Number
Manufacturer
Quantity
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Part Number:
pex8716-RPOTO-80BC G
Manufacturer:
PLX
Quantity:
850
PEX 8732 Highlights
© PLX Technology, www.plxtech.com
o 32-lane, 8-port PCIe Gen3 switch
o 27 x 27mm
o Typical Power: 5.84 Watts
o Standards Compliant
o High Performance
o Flexible Configuration
o Multi-Host & Fail-Over Support
o Quality of Service (QoS)
o Reliability, Availability, Serviceability
PEX 8732 Vitals
PEX 8732 Key Features
- Integrated 8.0 GT/s SerDes
- PCI Express Base Specification, r3.0
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
 performancePAK
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru w/ 132ns max packet
- Ports configurable as x1, x4, x8, x16
- Registers configurable with strapping pins,
- Lane and polarity reversal
- Compatible with PCIe 1.0a PM
- Configurable Non-Transparent (NT) port
- Failover with NT port
- Eight traffic classes per port
- Two Virtual Channels (VCs)
- Weighted round-robin source
 visionPAK
- 3 Hot-Plug Ports with native HP Signals
- All ports Hot-Plug capable thru I
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- INTA# and FATAL_ERR# signals
- Advanced Error Reporting
- Port Status bits and GPIO available
- JTAG AC/DC boundary scan
(compatible w/ PCIe r1.0a/1.1/2.0)
 Read Pacing (bandwidth throttling)
 Multicast
 Dynamic Buffer/FC Credit Pool
latency (x8 to x8)
EEPROM, I
port arbitration
 Per Port Performance Monitoring
 SerDes Eye Capture
 Error Injection and Loopback
(Hot-Plug Controller on every port)
 Per port payload & header counters
 Per port error diagnostics
2
, 676-ball PBGA package
2
C, or host software
2
C
Application:
Speed Bridge
PLX Products:
PEX8732 – 32-lane, 8-port PCIe Gen3 Switch
Key Benefit:
PCIe Gen 3 (8.0GT/s) speed
Release of PCIe Gen3 specification
Now that the PCIe Gen3 specification has been finalized, the 8.0Gbps high speed
serial interconnect will become common place in all system architecture. This
comes as the widely adopted PCIe Gen2 designs continue and ramp into volume
production. With the design challenges to overcome moving to the faster
bandwidth, Gen3 is still months away from being embraced. However, Gen3
switches can be used to bridge the specification gap. PCIe Gen3 is required to be
backwards compatible with existing PCIe implementations (ie. support the Gen2
and Gen1 specifications).
A Gen3 Switch as a Speed Bridge
device built on 40nm technology. PEX8732 offers Multi-Host PCI Express
switching capability that enables users to connect multiple hosts to their respective
endpoints via scalable, high-bandwidth, non-blocking interconnection to a wide
variety of applications including servers, storage, communications, and graphics
platforms. The PEX8732 is well suited for fan-out, aggregation, and peer-to-peer
traffic patterns. This is the perfect solution when supporting PCI Express.
Create Gen3 slots with a Gen2 CPU
Page 1 of 2
The simple addition of the ExpressLane
answer. This will allow existing Gen2 host/devices to run
at the higher throughput Gen3 speeds when other Gen3
host/devices are available in the same system architecture.
It is a fast and seamless way to support the new 8.0Gbps
speed.
The PEX8732 is a 32-lane, 8-port PCIe Gen3 switch
TM
PEX8732 is the
Issue #85
13July11

Related parts for pex8716

pex8716 Summary of contents

Page 1

... Memory (RAM) Error Correction - INTA# and FATAL_ERR# signals - Advanced Error Reporting - Port Status bits and GPIO available  Per port error diagnostics - JTAG AC/DC boundary scan © PLX Technology, www.plxtech.com Application: Speed Bridge PLX Products: PEX8732 – 32-lane, 8-port PCIe Gen3 Switch Key Benefit: PCIe Gen 3 (8 ...

Page 2

... PLX Gen3 Switches Available Today PCI-SIG® Device Base Spec. r3.0 PEX8748 r3.0 PEX8747 r3.0 PEX8732 r3.0 PEX8724 r3.0 PEX8716 r3.0 PEX8712 Additional PLX Advantages  visionPAK o SerDes Eye Width & Height Capture o Per Port Performance Monitoring o Packet gernation to saturate x16 wide Gen3 port o Error Injection in the data path to system behavior ...

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