Highlights
© PLX Technology, www.plxtech.com
PEX8749 General Features
o 48-lane, 18-port PCIe Gen 3 switch
o 27 x 27mm
o Typical Power: 7.3 Watts
o Standards Compliant
o High Performance
o Integrated DMA Engine
o Multi-Host & Fail-Over Support
o Quality of Service (QoS)
o Reliability, Availability, Serviceability
PEX8749 Key Features
- Integrated 8.0 GT/s SerDes
- PCI Express Base Specification, r3.0
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 126ns max packet
- 2KB Max Payload Size
- Four DMA Channels
- Internal Descriptor Support
- DMA function independent from
- 64-bit Addressing
- Pre-fetch Descriptor Mode
- Stride Mode
- 2 Configurable Non-Transparent ports
- Failover with Non-Transparent port
- Up to 6 upstream/Host ports with 1+1 or
- Two Virtual Channels
- Eight traffic classes per port
- Weighted round-robin source
visionPAK
- 3 Hot-Plug Ports with native HP Signals
- All ports hot-plug capable thru I
- SSC Isolation on up to 12 ports
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- Advanced Error Reporting
- Port Status bits and GPIO available
- JTAG AC/DC boundary scan
(compatible w/ PCIe r1.0a/1.1 & 2.0)
Read Pacing (bandwidth throttling)
Multicast
Dynamic Buffer/FC Credit Pool
latency (x16 to x16)
transparent switch function
N+1 failover to other upstream ports
port arbitration
Per Port Performance Monitoring
SerDes Eye Capture
PCIe Packet Generator
Error Injection and Loopback
2
, 676-pin FCBGA package
performancePAK
2
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PEX8749, PCI Express Gen 3 Switch, 48 Lanes, 18 Ports
The ExpressLane™ PEX8749 device offers Multi-Host PCI Express switching
capability enabling users to connect multiple hosts to their respective
endpoints via scalable, high bandwidth, non-blocking interconnection to a
wide variety of applications including servers, storage, communications, and
graphics platforms. The PEX8749 is well suited for fan-out, aggregation,
and peer-to-peer traffic patterns.
Multi-Host Architecture
The PEX8749 employs an enhanced version of PLX’s field tested PEX8748
PCIe switch architecture, which allows users to configure the device in legacy
single-host mode or multi-host mode with up to six host ports capable of 1+1
(one active & one backup) or N+1 (N active & one backup) host failover. This
powerful architectural enhancement enables users to build PCIe based systems
to support high-availability, failover, redundant, or clustered systems.
High Performance & Low Packet Latency
The PEX8749 architecture supports packet cut-thru with a maximum
latency of 126ns (x16 to x16). This, combined with large packet memory,
flexible common buffer/FC credit pool and non-blocking internal switch
architecture, provides full line rate on all ports for performance-hungry
applications such as servers and switch fabrics. The low latency enables
applications to achieve high throughput and performance. In addition to low
latency, the device supports a packet payload size of up to 2048 bytes,
enabling the user to achieve even higher throughput.
Integrated DMA Engine
The PEX8749 boasts a versatile and powerful built-in DMA engine. The
DMA engine removes the burden of having to move data between devices
away from the processor – allowing the processor to perform computational
tasks instead. The four DMA channels can support high data rate transfers
between I/O devices connected to any of the switch’s ports. Additionally, the
DMA engine in the PEX8749 can be used to complement the DMA engine in
the processor by providing additional DMA channels for higher performance.
Data Integrity
The PEX8749 provides end-to-end CRC (ECRC) protection and Poison bit
support to enable designs that require end-to-end data integrity. PLX also
supports data path parity and memory (RAM) error correction circuitry
throughout the internal data paths as packets pass through the switch.
Flexible Configuration
The PEX8749’s 18 ports can be
configured to lane widths of x1, x2, x4,
x8, or x16. Flexible buffer allocation,
along with the device's flexible packet
flow control, maximizes throughput for
applications where more traffic flows in
the downstream, rather than upstream,
direction. Any port can be designated as
the upstream port, which can be changed
dynamically. Figure 1 shows some of the
PEX8749’s common port configurations
in legacy Single-Host mode.
Page 1 of 5
Figure 1. Single-Host Port Configurations
6 x4
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4 x8
8 x2
x8
x16
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17 x2 or x1
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10 x4
x8
x4
