wm8802scft/v Wolfgang Knap, wm8802scft/v Datasheet
wm8802scft/v
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wm8802scft/v Summary of contents
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Digital Audio Interface Transceiver DESCRIPTION The WM8802 is a digital audio interface transceiver conforming to IEC 60958/61937 and EIAJ CP-1201. The device supports data sampling input rates 192 kHz. Data input to the serial digital audio ...
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WM8802 DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................7 ELECTRICAL CHARACTERISTICS ......................................................................7 DC CHARACTERISTICS............................................................................................... 7 AC CHARACTERISTICS............................................................................................... 8 MICROCONTROLLER INTERFACE AC CHARACTERISTICS ..................................... 9 DEVICE ...
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... RXOUT 1 RXO 2 RX1 3 RX2 4 RX3 5 DGND 6 DVDD 7 RX4 8 RX5/ RX6/VI DVDD 11 DGND ORDERING INFORMATION DEVICE TEMPERATURE RANGE WM8802SCFT RERR 35 INT 34 CKST 33 AUDIO/VO 32 EMPH/UO 31 DGND DVDD 30 XIN 29 XOUT 28 XMCK 27 DVDD 26 DGND PACKAGE 0 to +70oC ...
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WM8802 PIN DESCRIPTION PIN NAME 1 RXOUT Digital Output 2 RX0 Digital Input 3 RX1 Digital Input 4 RX2 Digital Input 5 RX3 Digital Input 6 DGND 7 DVDD 8 RX4 Digital Input 9 RX5/VI Digital Input 10 RX6/UI Digital ...
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Product Preview PIN NAME 45 TBCK/GPIO1 Digital Input/Output Modulation 64fs bit clock input. General-purpose I/O input/output pin. 46 TLRCK/GPIO2 Digital Input/Output Modulation fs clock input. General-purpose I/O input/output pin. Digital Input/Output Modulation serial audio data input. General-purpose I/O input/output pin. ...
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WM8802 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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Product Preview RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltage AVDD, DVDD Input voltage range 1 Input voltage range 2 Operating temperature Notes: 1. RX1, RBCK, RLRCK, XIN pins TMCK/GPIO0, TBCK/GPIO1, TLRCK/GPIO2, TDATA/GPIO3, TXO/GPIOEN pins 2. RX0, RX2, RX3, RX4, RX5/VI, RX6/UI ...
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WM8802 AC CHARACTERISTICS Test Conditions o AC Characteristics AVDD = DVDD = 3.3V, AGND = DGND = 0V a PARAMETER RX0 TO RX6 sampling frequency XIN clock frequency XIN clock frequency RMCK clock frequency RMCK ...
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Product Preview MICROCONTROLLER INTERFACE AC CHARACTERISTICS Test Conditions o I/F AC Characteristics AVDD = DVDD = 3.3V, AGND = DGND = 0V a PARAMETER XMODE pulse width, Low pulse width, Low INT CL pulse width, ...
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WM8802 DEVICE DESCRIPTION INITIAL SYSTEM SETTINGS SYSTEM RESET (XMODE) The system operates normally when XMODE is set to High after applying a supply voltage of 3.0V or greater. Following power ON, the system is reset by setting XMODE to Low ...
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Product Preview CHIP ADDRESS SETTINGS (EMPHA/UO, AUDIO /VO) The WM8802 comes with a function to set a unique chip address to allow the use of several WM8802 on the same micro-controller bus. A 10k settings. This allows up to set ...
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WM8802 DEMODULATION FUNCTION MASTER/SLAVE SETTINGS ( CKST ) A master/slave function allows multi-channel synchronized transfer using multiple WM8802 devices. A 10k Set the master mode when using only one WM8802. When using multiple WM8802 devices, set one to the master ...
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Product Preview DESCRIPTION OF DEMODULATION FUNCTION The demodulation function operation settings are performed using RXOPR. CLOCKS PLL (LPF) The VCO (Voltage Controlled Oscillator) can be stopped if PLLOPR is set. Synchronization to frequencies from 32kHz to 192kHz and RMCK of ...
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WM8802 DEMODULATION FUNCTION WITHOUT USING PLL (TMCK) The WM8802 has a function to process input bi-phase data using an external clock (external synchronization function). In normal demodulation processing, the clock is generated in synchronization with data by the built-in PLL; ...
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Product Preview The oscillation amplifier can be stopped unnecessary. When operation is resumed it is recommended to return to the normal operation after an interval of 10ms or longer to allow the resonator oscillation to stabilise. XMCK ...
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WM8802 When the PLL changes from locked to unlocked status, the timing for switching the clock from the PLL source to the XIN source can be changed with XTWT[0:1 recommended to use these commands if noise occurs during ...
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Product Preview OUTPUT CLOCKS (RMCK, RBCK, RLRCK, SBCK, SLRCK) The WM8802 features two clock systems in order to supply the various clocks for the A/D converter, DSP and other peripheral devices. The clock output settings for the R and S ...
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WM8802 OUTPUT CLOCKS BLOCK DIAGRAM (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK) The relationships between the output clock and switch function are shown below. Master Clock Generator in the figure indicates the PLL source, TMCK source or the XIN source. The ...
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Product Preview Master Clock Generator XTAL Source 12.288MHz or 24.576MHz PLL Source 256fs or 512fs TMCK Source 256fs Figure 7 Clock Output Block Diagram w Lock / Unlock [PRSEL] 512fs / 256fs 256fs / 128fs 128fs / 64fs MUTE 12.288MHz ...
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WM8802 CLOCK SWITCH TRANSITION SIGNAL OUTPUT ( CKST ) CKST outputs Low when the output clock changes during PLL lock/unlock. In the lock-in stage (PLL locked following the detection of input data) the CKST Low pulse falls at the word ...
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Product Preview BI-PHASE SIGNAL INPUT / OUTPUT BI-PHASE SIGNAL INPUT RECEPTION RANGE The input data reception range depends on the PLL lock frequency setting set by PLLSEL. The relationship between this setting and the guaranteed reception range is shown below. ...
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WM8802 BI-PHASE SIGNAL INPUT CIRCUITS (RX0, RX1, RX2) If RX1, which has a built-in amplifier, is used as a coaxial input signal corruption may occur due to the influence of the adjacent RX0 and RX2 input pins. RX0 and RX2 ...
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Product Preview SERIAL AUDIO DATA INPUT/OUTPUT OUTPUT DATA FORMAT (RDATA) The output format is set with OFSEL[0:2 the initial output format setting. Right Justified outputs are only valid in master mode. Output data is output in ...
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WM8802 RLRCK (0) RBCK (0) RDATA (0) 1 MSB Figure 14 Data Output Timing – Right Justified SERIAL AUDIO DATA INPUT FORMAT (SDIN) SDIN bit serial digital audio data input pin. The format of the serial audio ...
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Product Preview SDIN ( MSB RLRCK (0) RBCK (0) RDATA ( MSB Figure 16 Serial Audio Data Input Timing – Left Justified SDIN (1) 1 RLRCK (0) RBCK (0) RDATA (0) 1 MSB Figure ...
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WM8802 OUTPUT DATA SWITCHING (SDIN, RDATA) RDATA demodulation data is output when the PLL is locked and the SDIN input is selected This switching is automatically performed according to the locked/unlocked status of the PLL. For details, see the timing ...
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Product Preview RX0 RX1 RX2 RX3 RX4 RX5 RX6 Figure 19 Data Block Diagram CALCULATION OF INPUT DATA SAMPLING FREQUENCY The input data sampling frequency is calculated using the XIN clock. When the oscillation amplifier automatically stops during PLL lock, ...
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WM8802 PLL LOCK ERROR The PLL becomes unlocked for input data that has lost bi-phase modulation regularity or input data where preambles B, M, and W cannot be detected. RERR goes High during the occurrence of a PLL lock error ...
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Product Preview PLL LOCK DATA ERROR RDATA output Low fs calculation result Low Channel status Low Validity flag Low User data Low Table 11 Data Processing upon Error Occurrence Notes: 1. Input parity error (A): Occurs 9 or more times ...
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WM8802 Internal clock signal Figure 21 Internal Lock Signal CHANNEL STATUS OUTPUT DATA CATEGORY SPECIFICATION BIT 1 OUTPUT ( AUDIO ) The AUDIO pin outputs bit 1 of the channel status indicating that the input bi-phase data is PCM audio ...
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Product Preview OTHER OUTPUTS VALIDITY FLAG OUTPUT (VO) The validity flag can be output from the AUDIO /VO pin by selecting the AUDIO /VO output with VOSEL. The validity flags transferred at each sub-frame are output as indicated in the ...
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WM8802 IEC61937, DTS-CD/LD DETECTION FLAG OUTPUT A function to output IEC61937 and DTS-CD/LD detection flags for non-PCM data is provided. When the UNPCM non-PCM signal output setting is selected, as well as an indication on the AUDIO pin, an interrupt ...
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Product Preview DESCRIPTION OF MODULATION FUNCTION AND GENERAL-PURPOSE I/OS MODULATION FUNCTION USAGE METHOD INITIAL SETTING The modulation function and general-purpose I/O port function cannot be used simultaneously because they share the same pins. INT should be pulled down with a ...
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WM8802 TLRCK (I) TBCK (I) TDATA ( MSB bits Figure 26 Data Input Timing – Left Justified Data Input VALIDITY FLAG INPUT (VI) Validity flags can be input from RX5/VI by switching the RX5/VI ...
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Product Preview USER DATA INPUT (UI) User data can be input from RX6/UI by switching the RX6/UI input contents using UISEL. The user data write timing is shown below. Internal latch signal Figure 28 User Data Input Timing MODULATED OUTPUT ...
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WM8802 GENERAL PURPOSE I/O (GPIO0, GPIO1, GPIO2, GPIO3, GPIOEN) INITIAL SETTINGS The modulation function and general-purpose parallel I/O’s share the same pins and therefore cannot be used simultaneously. INT should be pulled down with a 10k I/O’s. For the setting ...
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Product Preview MICRO-CONTROLLER INTERFACE ( INT , CL, CE, DI, DO) DESCRIPTION OF MICRO-CONTROLLER INTERFACE INTERRUPT OUTPUT ( INT ) Interrupts are output when a change has occurred in the PLL lock status or output data information. Interrupt output is ...
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WM8802 REGISTER INPUT/OUTPUT CONTENTS Function setting data input write CS data input Interrupt data output fs data output CS data output Pc data output Table 17 Relationship between Register Input/Output Contents and CCB Addresses DATA WRITE METHOD Input is performed ...
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Product Preview Hi-Z Figure 31 Input Timing Chart (Normal, High Clock Hi-Z Figure 32 Output Timing Chart (Normal, Low Clock ...
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WM8802 WRITE DATA WRITE COMMAND LIST A list of the write commands is shown below. To write the commands shown in the following table, set the CCB address to 0xE8. ADD. SETTING ITEMS 0 All system setting TESTM 1 Demodulation ...
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Product Preview WRITE COMMAND DETAILS All system settings: REGISTER ADDRESS DI7 CCB address: 0xE8; 0 Command address: 0 DI15 TESTM SYSRST DOEN INTOPF RXOPR TXOPR TESTM RBCK and SBCK output Low and RLRCK and SLRCK output High when reset through ...
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WM8802 DEMODULATION FUNCTION System setting: REGISTER DI7 ADDRESS CCB address: 0xE8; 0 Command address: 1 DI15 0 UOSEL VOSEL AOSEL RXMON FSLIM [1:0] w DI6 DI5 DI4 DI14 DI13 DI12 DI11 0 FSLIM1 FSLIM0 RXMON EMPHA/UO pin ...
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Product Preview Master clock setting: REGISTER ADDRESS DI7 CCB address: 0xE8; 0 Command address: 2 DI15 AMPOPR1 AMPOPR0 PLLSEL XINSEL XMSEL [1:0] PLLOPR EXSYNC AMPOPR [1:0] If the PLL is stopped with PLLOPR during PLL lock, the output clocks are ...
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WM8802 R system output clock setting: REGISTER ADDRESS DI7 CCB address: 0xE8; 0 Command address: 3 DI15 XRLRCK1 XRLRCK0 PRSEL [1:0] XRSEL [1:0] XRBCK [1:0] XRLRCK [1:0] 3.072MHz is output from RBCK if the RMCK frequency is set lower than ...
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Product Preview S system output clock setting: REGISTER ADDRESS DI7 CCB address: 0xE8; 0 Command address: 4 DI15 XSLRCK1 PSBCK [1:0] PSLRCK [1:0] XSBCK [1:0] XSLRCK [1:0] w DI6 DI5 DI4 DI14 DI13 DI12 XSLRCK0 XSBCK1 XSBCK0 ...
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WM8802 Clock source; RDA TA output setting: REGISTER ADDRESS DI7 CCB address: 0xE8; 0 Command address: 5 DI15 0 SELMTD OCKSEL RCKSEL RDTSEL RDTSTA RDTMUT When the oscillation amplifier is set to permanent continuous operation using AMPOPR[0: changes ...
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Product Preview Digital data input/output port setting: REGISTER ADDRESS DI7 CCB address: 0xE8; 0 Command address: 6 DI15 RXOFF RISEL [2:0] ULSEL ROSEL [2:0] RXOFF ULSEL can be set when the oscillation amplifier is set to continuous operation with AMPOPR[0:1]. ...
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WM8802 Output data format setting: REGISTER ADDRESS DI7 CCB address; 0xE8; 0 Command address: 7 DI15 SLRCKP OFSEL [2:0] RBCKP RLRCKP SBCKP SLRCKP The data output format and RLRCK output polarity can be set independently. The RLRCH polarity is set ...
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Product Preview INT output contents setting: REGISTER ADDRESS DI7 CCB address: 0xE8; 1 Command address: 8 DI15 EMPF ERROR INDET FSCHG CSRNW UNPCM PCRNW SLIPO EMPF The channel status update flag compares the first 48 bits of data of the ...
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WM8802 RERR output setting: REGISTER ADDRESS DI7 CCB address: 0xE8, 1 Command address: 9 DI15 ERWT1 RESEL REDER XTWT [1:0] RESTA FSERR ERWT [1:0] Non-PCM data is reflected as data defined by AOSEL and matches the AUDIO pin output. Output ...
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Product Preview MODULATION FUNCTION System setting, general-purpose I/O data input: REGISTER ADDRESS DI7 CCB address: 0xE8; 1 Command address: 10 DI15 PI3 UISEL VISEL VMODE GPI0 GPI1 GPI2 GPI3 Set GPIOEN to Low if using general-purpose I/Os GPIO0 to GPIO3 ...
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WM8802 Digital audio input/output setting: REGISTER ADDRESS DI7 CCB address: 0xE8; 1 Command address: 11 DI15 0 TXDFS TXLRP TDTSEL TXMUT TXMOD [1:0] CHANNEL STATUS DATA WRITE CCB address is set to 0xE9 for channel status data write in the ...
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Product Preview REGISTER BIT NO. DESCRIPTION DI0 CAL Lower chip address DI1 CAU Higher chip address DI2 0 Reserved DI3 0 DI4 0 Data length setting DI5 0 DI6 0 DI7 0 Reserved Application DI8 Bit 0 Control DI9 Bit ...
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WM8802 READ REGISTER NAME DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 DO24 DO46 DO47 Table 20 Read Register 1 (Input detection, interrupt flag, ...
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Product Preview READ REGISTER OUTPUT CONTENTS REGISTER DO7 ADDRESS CCB address: 0XEA RXDET7 RXDET0 RXDET1 RXDET2 RXDET3 RXDET4 RXDET5 RXDET6 RXDET7 For RXDET0 to RXDET7 read, RXMON must be set to High first. w DO6 DO5 DO4 RXDET6 RXDET5 RXDET4 ...
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WM8802 READ REGISTER OUTPUT CONTENTS REGISTER DO15 ADDRESS CCB address; 0xEA DEMPF OERROR OINDET OFSCHG OCSRNW OUNPCM OPCRNW OSLIPO OEMPF The status of RERR and AUDIO is read according to RESEL and AOSEL settings regardless of the INT output setting ...
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Product Preview READ REGISTER OUTPUT CONTENTS REGISTER DO23 ADDRESS CCB address: 0xEA F4096 CSBIT1 IEC1937 DTS51 DTSES F0512 F1024 F2048 F4096 w DO22 DO21 DO20 F2048 F1024 F0512 Channel status bit 1 detection 0: PCM 1: Non-PCM IEC61937 burst preamble ...
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WM8802 READ REGISTER 2 (GENERAL-PURPOSE I/O INPUT CONTENTS, FS CALCULATION RESULT, FS COUNTER DATA) READ REGISTER OUTPUT CONTENTS REGISTER ADDRESS DO7 CCB address: 0xEB FSC3 GPO0 GPO1 GPO2 GPO3 FSC [3:0] FSC3 FSC2 FSC1 ...
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Product Preview READ REGISTER OUTPUT CONTENTS REGISTER ADDRESS DO15 CCB address: 0xEB FSDAT7 FSDAT [7:0] FSDAT [7:0] is the fs calculation counter value. The data length is 8 bits, FSDAT0 is LSB and FSDAT7 is MSB. The relation between the ...
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WM8802 READ REGISTER 4 (BURST PREAMBLE PC DATA) The burst preamble Pc data can be read with the demodulation function. The 16 bits of burst preamble Pc data are output as LSB. For read, the CCB address is set to ...
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Product Preview BURST PREAMBLE PC FIELD The burst preamble Pc field is shown below. For the latest information, check the standards issued by each licensee. REGISTER DO4 to 0 DO6, 5 DO7 DO12 to 8 DO15 to 13 Table 22 ...
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WM8802 RECOMMENDED EXTERNAL COMPONENTS Chip address setting Chip address setting Demodulation function master/slave setting Modulation/general-purpose I/O function selection Microcontroller Cc DVDD TMCK/GPIO0 TBCK/GPIO1 Analogue to Digital TLRCK/GPIO2 Digital Signal Processing TDATA/GPIO3 TXO/GPIOEN Coaxial Input Figure 34 ...
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Product Preview RECOMMENDED EXTERNAL COMPONENTS VALUES ELEMENT RECOMMENDED SYMBOL CONSTANT Cc 0 220 Table 23 Recommended Component Values ...
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WM8802 PACKAGE DRAWING FT: 48 PIN SQFP ( 1.0 mm Dimensions Symbols (mm) MIN NOM A ----- ----- ----- 0. ----- A 1.50 2 ----- ...
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