rt9006b Richtek Technology Corporation, rt9006b Datasheet - Page 8

• Manufacturer Part Number: rt9006b
• Description: Dual Regulator With Reset Function
• Manufacturer: Richtek Technology Corporation

RT9006A/B
Application Information
Detector Delay Time
The delay time (T
calculated from the formula :
V
is the CT pin sourcing current. C
the external capacitor from CT pin to GND.
Current limit
The RT9006 contains two independent current limiters,
which monitors and controls the pass transistor’ s gate
voltage, limiting the output current to a certain level. The
typical current limit level of channel 1 and channel 2 is
450mA and 600mA respectively.
Thermal Consideration
For continued operation, do not exceed absolute maximum
operation junction temperature 125°C. The maximum power
dissipation depends on the thermal resistance of IC
package, PCB layout, the rate of surroundings airflow and
temperature difference between junction to ambient. The
maximum power dissipation can be calculated by following
formula :
P
Where
T
125°C.
T
θ
The junction to ambient thermal resistance for SOP-8
(Exposed Pad) package is 75°C/W on the standard
JEDEC 51-7 (4 layers, 2S2P) thermal test board. The
copper thickness is 2oz. The maximum power dissipation
at T
P
(Exposed Pad) packages}
www.richtek.com
8
T
JA
J(MAX)
A
IN2
D(MAX)
D(MAX)
d
: The operated ambient temperature.
=
: The junction to ambient thermal resistance.
A
is the input voltage of channel 2 and the I
C
= 25°C can be calculated by following formula :
CT
: The maximum operation junction temperature
= ( T
= (125°C − 25°C) / 75 °C/W = 1.33W {SOP-8
x
0.8
J(MAX)
I
x V
CT
− T
d
IN2
) of Reset signal from V
A
) / θ
JA
CT
is the capacitance of
CT
OUT2
(2.6uA.Typ.)
can be
The maximum power dissipation depends on operating
ambient temperature for fixed T
θ
de-rating curves allows the designer to see the effect of
rising ambient temperature on the maximum power allowed.
PCB Layout Considerations
The thermal resistance θ
determined by the package design and the PCB design.
However, the package design had been designed. If
possible, it's useful to increase thermal performance by
the PCB design. The thermal resistance θ
decreased by adding a copper under the exposed pad of
SOP-8 (Exposed Pad)
As shown in Figure 2, the amount of copper area to which
the
performance. When mounted to the standard
(Exposed Pad)
copper area of pad under the
(Figure 2.b) reduces the θ
increasing the copper area of pad to 70mm
reduces the θ
JA
Figure 1. Derating Curves for
. For SOP-8 (Exposed Pad) packages, the Figure 1 of
2.2
1.8
1.6
1.4
1.2
0.8
0.6
0.4
0.2
SOP-8 (Exposed Pad)
2
1
0
0
Copper Area
70mm
50mm
30mm
10mm
Min. layout
16.25 32.5 48.75
2
2
2
2
JA
pad (Figure 2.a), θ
to 49°C/W.
Ambient Temperature (°C)
package.
Package
DS9006A/B-05
JA
JA
65
of
is mounted affects thermal
J(MAX)
to 64°C/W. Even further,
SOP-8 (Exposed Pad)
SOP-8 (Exposed Pad)
81.25 97.5 113.8 130
SOP-8 (Exposed Pad)
and thermal resistance
JA
is 75°C/W. Adding
4-Layers PCB
September 2007
2
(Figure 2.e)
JA
can be
SOP-8
is