sc488mltrt Semtech Corporation, sc488mltrt Datasheet - Page 18

• Manufacturer Part Number: sc488mltrt
• Description: Sc488 Complete Ddr1/2/3 Memory Power Supply
• Manufacturer: Semtech Corporation

feedback signal VTTS is critical. The trace from VTTS (pin
2) should be connected directly to the output capacitor that
is farthest from VTT (pin24); route this signal away from
noise sources such as the VDDQ power train or highspeed
digital signals.
The switcher power section should connect directly to the
ground plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses. Make all the connections on one side
of the PCB using wide copper fi lled areas if possible. Do
not use “minimum” land patterns for power components.
Minimize trace lengths between the gate drivers and the
gates of the MOSFETs to reduce parasitic impedances
(and MOSFET switching losses); the low-side MOSFET is
most critical. Maintain a length to width ratio of <20:1 for
gate drive signals. Use multiple vias as required by current
handling requirement (and to reduce parasitics) if routed
on more than one layer. Current sense connections must
always be made using Kelvin connections to ensure an
accurate signal. The layout can be generally considered
in three parts; the control section referenced to VSSA, the
VTT output, and the switcher power section.
Looking at the control section fi rst, locate all components
referenced to VSSA on the schematic and place these
components at the chip. Connect VSSA using a wide
(>0.020”) trace. Very little current fl ows in the chip ground
therefore large areas of copper are not needed. Connect the
VSSA pin directly to the thermal pad under the device as
the only connection from PGND1 and PGND2 from VSSA.
Decoupling capacitors for VCCA/VSSA and VDDP/PGND1
should be placed is as close as possible to the chip. The
feedback components connected to FB, along with the
VDDQ sense components, should also be located at the
chip. The feedback trace from the VDDQ output should
route from the top of the output capacitors, in a quiet layer
back to the FB components.
Next, looking at the switcher power section, there are a few
key guidelines to follow:
1.
2.
© 2006 Semtech Corp.
POWER MANAGEMENT
Application Information (Cont.)
There should be a very small input loop, well
decoupled.
The phase node should be a large copper pour, but
still compact since this is the noisiest node.
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3.
Finally, connecting the control and switcher power sections
should be accomplished as follows:
1.
2.
3.
4.
Input power ground and output power ground should
not connect directly, but through the ground planes
instead.
Route VDDQ feedback trace in a “quiet” layer, away
from noise sources.
Route DL, DH and LX (low side FET gate drive, high
side FET gate drive and phase node) to the chip using
wide traces with multiple vias if using more than one
layer. These connections are to be as short as possible
for loop minimization, with a length to width ratio less
than 20:1 to minimize impedance. DL is the most
critical gate drive, with power ground as its return
path. LX is the noisiest node in the circuit, switching
between VBAT and ground at high frequencies, thus
should be kept as short as practical. DH has LX as its
return path.
BST is also a noisy node and should be kept as short
as possible.
Connect PGND1 pins on the chip directly to the VDDP
decoupling capacitor and then drop vias directly to
the ground plane. Locate the current limit resistor
(if used) at the chip with a kelvin connection to the
phase node.
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SC488