ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet
ox16pci958
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ox16pci958 Summary of contents
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... I/O and memory accesses for control of the UART. The data for configuration space is read from a small external serial EEPROM at start-up, together with information on how the OX16PCI958 should be set up. External—Free Release OX16PCI958 DS-0022—Nov 2005 Octal UART C— ...
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... Example EEPROM Data 6. Clock/Oscillator Pins 7. Operating conditions 7.1. Recommended Operating Conditions 7.2. DC Characteristics 8. I/O electrical & timing specifications 9. Package information 10. Glossary 11. Ordering information 12. Contact Details DS-0022 Nov 05 External—Free Release OX16PCI958 DATA SHEET ...
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... Note: The connections between the UART RAM blocks and each of the UARTs are omitted for clarity. DS-0022 Nov 05 EEPROM Signals EEPROM Reader PCI Side Registers PCI Clock Domain Local Clock Domain UART UART I/O Switching I/O Banks External—Free Release OX16PCI958 DATA SHEET UART UART UART UART Page 3 ...
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... AD28 152 AD27 153 AD26 154 AD25 155 VDDP 156 AD24 157 VSS 158 C/BE#3 159 IDSEL 160 DS-0022 Nov 05 QFP PIN OX16PCI958 External—Free Release OX16PCI958 DATA SHEET 80 CTS5 79 XTALO 78 XTALI 77 VSS 76 DTR5 75 RI5 74 VDD 73 DCD6 72 DSR6 71 SIN6 70 RTS6 69 VSS ...
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... DS-0022 Nov 05 Table 1 Pin Descriptions the PCI connector. External—Free Release OX16PCI958 DATA SHEET Dir Description PCI bus signals Chip configuration Local clock Local side Power and ground pins I/O Page 5 ...
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... DSR 1 SIN 2 RTS 3 SOUT 4 CTS 5 DTR DCD 0 DSR 1 SIN 2 RTS 3 SOUT 4 CTS 5 DTR External—Free Release OX16PCI958 DATA SHEET Bank Pin Dir Name DCD 96 I DSR 95 I SIN 94 O RTS 92 O SOUT 91 I CTS 90 O DTR ...
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... The serial EEPROM reader can access any internal address Table 5 lists the PCI register offsets. DS-0022 Nov 05 Table 4 PCI Address Mapping PCI bridge configuration EEPROM control, power management UART, SISR UARTs SISR External—Free Release OX16PCI958 DATA SHEET 00h to 2Fh 30h to 3Fh 40h to 7Fh 80h to BFh C0h to CFh Page 7 ...
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... UART 7 registers 8-9 other RFU Notes: Writes to undefined internal addresses are ignored, and reads from undefined internal addresses return zero For shared address ranges, the SISR takes priority over the UARTs DS-0022 Nov 05 Table 5 Register Offsets External—Free Release OX16PCI958 DATA SHEET Page 8 ...
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... Global pre- 50h RFU1 divider EEPROM-Control Register The OX16PCI958 automatically takes control of the EECS, EECK and EEDIO pins after a deassertion of the host bus RESET signal, in order to read in configuration data. Afterwards, the signals may be controlled though accesses to this register. Field (Bits) Description EET2 (7) High— ...
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... Table 9 to bits 5 and 2: Table 9 Clock Pre-Division Values The above register settings are recommended for backwards compatibility, but Table 10 shows how the actual control logic operates. Table 10 Clock Division Logic enables the External—Free Release OX16PCI958 DATA SHEET Value Divisor F6h 8 F2h 4 D6h 2 ...
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... INTA# is only asserted when the Interrupt Disable bit in Command is 0 & this Interrupt Status bit Setting the Interrupt Disable bit has no effect on the state of this bit. External—Free Release OX16PCI958 DATA SHEET Revision ID Cache line size Capabilities pointer ...
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... I/O range defined by this BAR map to internal UARTs at internal addresses 80h-BFh. Base Address Register 3 This base address register is for a mapping of 16 bytes in I/O space. Accesses made to the I/O range defined by this BAR map to unused internal addresses C0h-CFh. External—Free Release OX16PCI958 DATA SHEET for access to local Page 12 ...
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... Bits Description 10 0—writing 10b to the PowerState bits in PMCSR (see below) leaves PowerState unchanged 9 0—writing 01b to the PowerState bits in the PMCSR (see below) leaves PowerState unchanged External—Free Release OX16PCI958 DATA SHEET Page 13 ...
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... Extensions register at offset 46h is read-only, and always returns the value 00h. DS-0022 Nov 05 The Power Management Data register at Control/Status offset 47h is read-only, and returns a value which depends on which data value has been selected using PMCSR [12:9]. External—Free Release OX16PCI958 DATA SHEET Page 14 ...
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... PMDS(3:0) and PMDS(7:4) contain eight 2-bits, packed as shown below, returned as a value for bits 14:13 in PMCSR when PMCSR [12: where n references PMDSn (see section 3.3). DS-0022 Nov 05 Table 12 Address Map External—Free Release OX16PCI958 DATA SHEET Default Value 15h* 14h* 38h* 95h* ...
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... OXFORD SEMICONDUCTOR LTD. 4. UART FUNCTION Each UART in the OX16PCI958 is identical. The depth of the FIFOs is 32 bytes. Each UART converts between RS232-format serial data on separate transmit and receive lines, and byte-wide I/O writes and reads on the host interface. Malformed incoming serial data is flagged along with the data in the receive FIFO ...
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... DS-0022 Nov 05 Mnem. IIR LSR MSR CIDR RFLR TFLR Mnem. SCR ISCR External—Free Release OX16PCI958 DATA SHEET Page 17 ...
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... Receive FIFO flow-control trigger register RITR Receive FIFO interrupt trigger register TITR Transmit FIFO interrupt trigger register CPR Clock prescaler register WER Wake event enable register - Reserved for future use – do not read or write External—Free Release OX16PCI958 DATA SHEET Page 18 ...
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... Bit 4 Bit 3 Clock Clock Hold CTS select bit 1 select bit 0 RFU RFU RFU Bit 5 Bit 4 Bit 3 External—Free Release OX16PCI958 DATA SHEET Bit 2 Bit 1 Bit 0 Data Bit 0 Data Bit 2 Data Bit 1 (LSB) Data Bit 2 Data Bit 1 Data Bit 0 Bit 2 Bit 1 Bit 0 ...
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... Bit 3 Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 RFU SIN# DCD ‡ These bits are always 0 when FIFOs are External—Free Release OX16PCI958 DATA SHEET Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit SF=4 RFU RFU Enable Force AFC RFU ...
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... LCR. Note if parity is used (LCR3) then the polarity of parity Low LCR4 is required. Low The receiver timing is supplied by the baud clock generator. External—Free Release OX16PCI958 DATA SHEET Reset Control FIFO Reset State Reset FIFO empty FCR1–FCR0 FCR0 Reset FIFO empty FCR1– ...
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... After the next THRE, set the break 3. When TEMT is set to high, wait for the transmitter to be idle 4. Clear the break when the transmission has to be re-established. External—Free Release OX16PCI958 DATA SHEET Description No parity Odd parity Even parity Set parity Cleared parity ...
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... The contents of the IIR are indicated in the table below. Bits Description 7:6 Set when FCR0 is set, i.e., the UART FIFO mode 3:1 Identifies the highest-priority interrupt currently active, as indicated in Table 23. 0 Cleared when any interrupt is active; set when no interrupt sources are active External—Free Release OX16PCI958 DATA SHEET Page 23 ...
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... At least quarter- full At least half-full At least seven- eighths full External—Free Release OX16PCI958 DATA SHEET Clear Mechanism Read LSR Read RBR Read RBR until FIFO drops below the trigger level Read IIR or write to THR Read MSR - FIFO Interrupt Mode ...
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... FIFO. Transmit FIFO Level Register (TFLR) This read-only between 0 and 32, relating to the number of available spaces in the transmit FIFO. External—Free Release OX16PCI958 DATA SHEET Effect on THRE interrupt Interrupt cannot occur until IER1 set Interrupt is set immediately if transmit FIFO empty ...
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... SIN CTS# DTR# DCD# RI# loop-back signal input 1 pin 0 MCR4 External—Free Release OX16PCI958 DATA SHEET is controlled by the signal which normally goes to this output pin: output is forced high SOUT DTR# DSR# OUT1# OUT2# ‘1’ output pin 1 Normal UART ...
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... SIN Serial Flow CTS# RTS# Control External—Free Release OX16PCI958 DATA SHEET Description Set when the DCD# input is low. In loopback mode (MCR4 is set), MSR7 reflects the value last written to MCR3 Set when the RI# input is low. In loopback mode, MSR6 reflects the value last written to MCR2 Set when the DSR# input is low ...
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... RTS# is asserted when the receive FIFO is below a certain trigger level, and deasserted when the receive FIFO above that trigger level. The OX16PCI958 UARTs support the setting of the trigger level to four predefined levels using FCR7:6 and also allow a precise value to be set using RFTR. ...
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... Write the value X to DLM Set X Set bit the exclusive-or of bit 7 and bit IER4 is set, the chip is an OX16PCI958 or a future device with the same extended- register system. Write 2 to IRSR and read CIDR to identify the device type. If IER4 is clear, the chip is not a known device ...
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... This value is determined using a round-robin algorithm. There is no requirement to use the SISR function, UARTs may be serviced in any order— the SISR is only included as an aid to fair servicing of the ports. External—Free Release OX16PCI958 DATA SHEET Page 30 ...
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... Any serial EEPROM with a 16-bit data and Microwire-compatible read instruction, where the number of address bits is either should be suitable for use with the OX16PCI958. The EEPROM does not have to have a sequential read feature. This means that most 93C46, 93C56 and 93C66 parts should be suitable ...
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... EEPROM Data Format The contents of the EEPROM are used to generate a series of internal register writes in the OX16PCI958 – the data specifies a sequence of addresses to be written to and the byte to be written. Table 30 shows how the data in the EEPROM is organized. Address Bits 15:8 of data 00h sync ...
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... Set IRSR for UART 0 back that the scratch register is seen at offset 7 by default, for backwards compatibility 5. Switch the safety catch for UART 0 back on Table 31 shows how the example information above translates to EEPROM data. DS-0022 Nov 05 External—Free Release OX16PCI958 DATA SHEET Page 33 ...
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... FFh 00h 10h 1Ch 00h 80h External—Free Release OX16PCI958 DATA SHEET Notes sync. byte and end address VID lower byte VID upper byte SVID lower byte SVID upper byte DID lower byte DID upper byte SDID lower byte ...
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... LOCK SCILLATOR INS The OX16PCI958 provides a clock input and a logically inverted output suitable for driving a crystal oscillator as shown below Alternatively, the XTALI pin may be driven from an external clock signal, and the XTALO pin used as an optional clock output. ...
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... IOZ DS-0022 Nov 05 Table 32 Absolute Maximum Ratings Min -0.3 -55 Min 4.5 3 14.7 Min 0.7 x VDD -10 Min 2.0 -10 Min 2.4 -10 External—Free Release OX16PCI958 DATA SHEET Max Unit 7.0 V VDD + 0 µA 150 ºC Max Unit 5 ºC 150 ºC 331/3 MHz ...
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... OXFORD SEMICONDUCTOR LTD. 8. I/O & ELECTRICAL TIMING SPECIFICATIONS The host interface timings comply with all requirements of PCI specifications. In DS-0022 Nov 05 External—Free Release OX16PCI958 DATA SHEET Page 37 ...
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... IEEE 1284-2000, when fitted with an external 22 Ω series resistor (all signals) and 1.2 kΩ pull-up resistors (input and bi-directional pins) Power/power voltage— power or I/O pin is connected to the 3.3/5V I/O group used for the PCI interface, or the 5V group used for the other I/Os DS-0022 Nov 05 External—Free Release OX16PCI958 DATA SHEET Page 38 ...
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... CMOS 2-11 7 CMOS 2-11 7 CMOS 2-11 7 CMOS 2-11 7 CMOS - - 7 CMOS 2-11 7 CMOS 2-11 7 CMOS 2-11 7 CMOS 2-11 7 CMOS 2-11 7 CMOS 2-11 7 External—Free Release OX16PCI958 DATA SHEET Signalling/ power voltage ( PCI Universal 3.3/5 3.3/5 - PCI Universal 3.3/5 - PCI Universal 3.3/5 - PCI Universal 3.3/5 - PCI Universal 3.3/5 - PCI Universal 3.3/5 - PCI Universal 3.3/5 - PCI Universal 3.3/5 3.3/5 - PCI Universal 3.3/5 - PCI Universal 3 ...
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... PU TTL TTL TTL - 20 PU TTL - 20 PU TTL External—Free Release OX16PCI958 DATA SHEET Signalling/ power voltage ( PCI Universal 3.3/5 - PCI Universal 3.3/5 3.3/5 3.3/5 - global tri-state control Tie to GND - - IEEE 1284 level IEEE 1284 level 2 - IEEE 1284 level 2 IEEE 1284 level 2 ...
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... PU TTL TTL - 20 PU TTL - 20 PU TTL - 20 PU TTL - 20 PU TTL External—Free Release OX16PCI958 DATA SHEET Signalling/ power voltage (in V) IEEE 1284 level 2 - IEEE 1284 level IEEE 1284 level 2 IEEE 1284 level 2 IEEE 1284 level ...
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... Although the PME# pin is an open-collector output not suitable for direct connection to the PCI bus. The PME# pin must be isolated from the host system when the OX16PCI958 power source is absent, so that it does not cause unwanted wake events. See section 7 of the PCI Bus Power Management Interface Specification, revision 1 ...
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... PCB, as shown in Figure 7. PIN Min 0. 0.22 Lead coplanarity Plastic body dimensions do not include flash or protrusion, max allowable 0.25 mm per side. DS-0022 Nov 05 Figure 7 OX16PCI958 Package Lead coplanarity Max Basic 4.10 3.60 0.23 31.20 28.00 31.20 28.00 0.50 1.03 0.65 0.40 0.10 External—Free Release OX16PCI958 DATA SHEET E ...
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... Quad Flat Pack RFU Reserved for future use: register bits described as RFU should be cleared during writes, and ignored during reads. They will be clear when read, but for future compatibility this should not be assumed. RO Read-only DS-0022 Nov 05 External—Free Release OX16PCI958 DATA SHEET Page 44 ...
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... OXFORD SEMICONDUCTOR LTD. 11. O RDERING INFORMATION OX16PCI958-PQAG DS-0022 Nov 05 RoHS compliant Revision Package Type – 160 QFP External—Free Release OX16PCI958 DATA SHEET Page 45 ...
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... C D ONTACT ETAILS Oxford Semiconductor Ltd. 25 Milton Park Abingdon Oxfordshire OX14 4SH United Kingdom Telephone: Fax: Sales e-mail: Tech support e-mail: Web site: DS-0022 Nov 05 +44 (0)1235 824900 +44 (0)1235 821141 sales@oxsemi.com support@oxsemi.com http://www.oxsemi.com External—Free Release OX16PCI958 DATA SHEET Page 46 ...