as7c33128pfs32a-166tqi Alliance Memory, Inc, as7c33128pfs32a-166tqi Datasheet
as7c33128pfs32a-166tqi
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as7c33128pfs32a-166tqi Summary of contents
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... SSQ V 27 DDQ / Note: Pins 1,30,51,80 are NC for ×32 AS7C33128PFS32A AS7C33128PFS32A –133 –100 7.5 10 133 100 4 5 425 325 100 Copyright © Alliance Semiconductor. All rights reserved. DDQ DQP / ...
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... WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High). • Master chip enable CE0 blocks ADSP, but not ADSC. AS7C33128PFS32A and AS7C33128PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × TQFP package. ...
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Signal descriptions I/ Signal O Properties Description CLK I CLOCK Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock. A0–A16 I SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. ...
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Synchronous truth table CE0 CE1 CE2 ADSP ADSC ...
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TQFP thermal resistance Description Thermal resistance Test conditions follow standard test methods and * (junction to ambient) procedures for measuring thermal impedance, per EIA/ Thermal resistance * (junction to top of case) * This parameter is sampled. DC electrical characteristics ...
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Timing characteristics over operating range Parameter Clock frequency Cycle time (pipelined mode) Cycle time (flow-through mode) Clock access time (pipelined mode) Clock access time (flow-through mode) Output enable LOW to data valid Clock HIGH to output Low Z Data output ...
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Timing waveform of read cycle CLK t ADSPS t ADSPH ADSP t ADSCS ADSC Address GWE, BWE t CSS t CSH CE0, CE2 CE1 t ADVS t ADVH ADV OE ...
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Timing waveform of write cycle t CH CLK t ADSPS t ADSPH ADSP ADSC Address BWE BW[a:d] t CSS t CSH CE0, CE2 CE1 ADV OE Data In D(A1) Note: Ý = XOR when MODE ...
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Timing waveform of read/write cycle CLK t ADSPS t ADSPH ADSP Address A1 GWE CE0, CE2 CE1 ADV OUT (pipeline mode) t CDF D OUT (flow-through mode) Note: Ý = XOR when MODE = HIGH/No Connect; ...
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AC test conditions • Output load: see Figure B, except for t • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. • Input ...
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... Ordering information –166 MHz AS7C33128PFS32A-166TQC AS7C33128PFS32A-150TQC AS7C33128PFS32A-166TQI AS7C33128PFS32A-150TQI AS7C33128PFS36A-166TQC AS7C33128PFS36A-150TQC AS7C33128PFS36A-166TQI AS7C33128PFS36A-150TQI Part numbering guide AS7C 33 128 1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33=3.3V 3.Organization: 128=128K 4.Pipeline-Flowthrough (each device works in both modes) 5.Deselect: S=Single cycle deselect 6.Organization: 32=x32; 36=x36 7.Production version: A=first production version 8 ...
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... This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components. ...