lv8095lq Sanyo Semiconductor Corporation, lv8095lq Datasheet - Page 6

• Manufacturer Part Number: lv8095lq
• Description: For Vcms Constant-current Driver Ic
• Manufacturer: Sanyo Semiconductor Corporation

I
Start and stop conditions
The I
data transfer operation.
When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is
started when SDA is changed from high to low while SCL and SDA are high.
Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is
high.
Data transfer and acknowledgement response
After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I
unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave
address and to the command (R/W) indicating the transfer direction of the subsequent data. However, this IC is provided
with only a write mode for receiving the data. Every time 8 bits of data for each byte are transferred, the ACK signal is
sent from the receiving end to the sending end. Immediately after the clock pulse of SCL bit 8 in the data transferred has
fallen to low, SDA at the sending end is released, and SDA is set to low at the receiving end, causing the ACK signal to be
sent. When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status,
the receiving end releases SDA at the falling edge of the ninth SCL clock.
2
C bus transmission method
2
C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a
(WRITE)
SDA
SCL
Start
SDA
SCL
M
S
B
A1
Start condition
A2 A3 A4 A5 A6 A7 0
Slave address
1st byte
th1
SCL
SDA
ts2
L
S
B
W
A
C
K
PD X D7 D6 D5 D4 D3 D2
LV8095LQ
M
S
B
X : DON'T CARE
th2
2nd byte
Data
S
B
L
C
A
K
D1 D0 X X X X X X
M
S
B
Stop condition
3ed byte
ts3
Data
S
B
L
A
C
K
Stop
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2
C bus, a