as3588a austriamicrosystems, as3588a Datasheet - Page 2

• Manufacturer Part Number: as3588a
• Description: Digital Time/space Crosspoint Switch
• Manufacturer: austriamicrosystems

Data Sheet
Pinout Configuration
Pin Description
Rev. 3.1
17 - 24 13 - 16,
8 - 15
1 - 4
DIP
16
25
OUT PCM3 .
OUT PCM2 .
OUT PCM 1 .
OUT PCM0 .
5
6
7
INP PCM7
INP PCM6
INP PCM5
INP PCM4
INP PCM3
INP PCM2
INP PCM1
INP PCM0
CLOCK
SYNC
N.C. .
VDD
D7
D6
D5
D4
40 - 43
44, 12,
17, 33,
18 - 21
3 - 10
QFP
39
11
22
1
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AS3588AP
Power
Type
OP
OP
I/O
IP
IP
IP
-
OUTPCM3 to
INPPCM7 to
OUTPCM0
INPPCM0
D7 to DO
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Symbol
CLOCK
SYNC
VDD
N.C.
DR
Figure 2: Pinout 40 pin DIP and 44 pin QFP
OUT PCM4
OUT PCM5
OUT PCM6
OUT PCM7
RD
WR
CS1
CS2
RESET
VSS
C/D
A1
S1
A2
S2
DR
D0
D1
D2
D3
Description
PCM Outputs 3 to 0.
These are open drain outputs for four primary rate PCM output
streams.
Unused Pin
Master Clock Input
This signal is the timing reference for all internal operations. The PCM
bit cell boundaries lie on the alternate rising edges of this clock.
Synchronization Input
This is an edge sensitive input for frame synchronization in the PCM
bit stream with a typical repetition rate of 8 kHz. The rising edge
determines the start of a new frame.
PCM Inputs 7 to 0
These are the inputs for primary rate PCM input streams
Positive Supply Voltage
Data Bus I/O Port.
These are the bi-directional data pins to the microprocessor interface.
Only 5 bits are used when data is written into AS3588A (D4 to D0)
Data Ready Output.
This active high signal goes low for signalling purposes
Page 2 of 15
INP PCM7
INP PCM6
INP PCM5
INP PCM4
INP PCM3
INP PCM2
INP PCM1
INP PCM0
CLOCK
SYNCN
V
DD
1
6
AS3588AQ
39
17
28
NC
WRN
CS1N
CS2N
RESETN
Vss
C/DN
A1
S1
A2
S2
AS3588A
July 1999