as5050 austriamicrosystems, as5050 Datasheet

no-image

as5050

Manufacturer Part Number
as5050
Description
Low Power 10-bit Magnetic Rotary Encoder
Manufacturer
austriamicrosystems
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
as5050A-BQFM
Manufacturer:
AMS
Quantity:
201
A S 5 0 5 0
L o w P o w e r 1 0 - B i t M a g n e t i c R o t a r y E n c o d e r
1 General Description
The AS5050 is a single-chip magnetic rotary encoder IC with low
voltage and low power features.
It includes 4 integrated Hall elements, a high resolution ADC and a
smart power management controller.
The angle position, alarm bits and magnetic field information are
transmitted over a standard 3-wire or 4-wire SPI interface to the host
processor.
The AS5050 is available in a small QFN 16-pin 4x4x0.85mm
package and specified over an operating temperature of -40ºC to
80ºC.
Figure 1. AS5050 Block Diagram
www.austriamicrosystems.com
Datasheet
VDD
Power Management
Hall Sensors
VSS
AS5050
ADC
Revision 1.12
mode
Wire
2 Key Features
3 Applications
The device is ideal for Servo motor control, Input device for battery
operated portable devices, and Robotics.
MOSI
- < 8mA (avg) @ 620µs readout interval
- < 5mA (avg) @ 1ms readout interval
- < 500µA (avg) @ 10ms readout interval
- < 53µA (avg) @ 100ms readout interval
10-bit resolution
Standard SPI interface, 3 or 4 wire
3.0 to 3.6 V core voltage, 1.8 to 3.6 V peripheral supply voltage
Automatic wakeup over SPI interface
Interrupt output for conversion complete indication
Low power mode:
Small size 16-pin QFN (4x4x0.85mm)
SPI Interface
Cordic
MISO
SCK
SS/
EN_INT/
INT/
VDDp
1 - 22

Related parts for as5050

as5050 Summary of contents

Page 1

... General Description The AS5050 is a single-chip magnetic rotary encoder IC with low voltage and low power features. It includes 4 integrated Hall elements, a high resolution ADC and a smart power management controller ...

Page 2

... Reading an Angle ........................................................................................................................................................................ 7 7.1.3 Low Power Mode ......................................................................................................................................................................... 7 7.1.4 Interrupt Chaining ........................................................................................................................................................................ 7 7.2 SPI Communication.............................................................................................................................................................................. 8 7.2.1 Command Package ..................................................................................................................................................................... 8 7.2.2 Read Package (Value Read from AS5050) ................................................................................................................................. 8 7.2.3 Write Data Package (Value Written to AS5050) .......................................................................................................................... 9 7.2.4 Register Block.............................................................................................................................................................................. 9 7.2.5 SPI Interface Commands........................................................................................................................................................... 10 8 Application Information ........................................................................................................................................................... 8.1 SPI Interface....................................................................................................................................................................................... 14 8.1.1 SPI Interface Signals (4-Wire Mode, Wire_mode = 1)............................................................................................................... 14 8.1.2 SPI Timing ................................................................................................................................................................................. 15 8.1.3 SPI Connection to the Host µ ...

Page 3

... AS5050 Datasheet - Pin Assignments Figure 2. Pin Assignments (Top View) MOSI MISO SCK SS/ 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Number Pin Name 1 MOSI 2 MISO 3 SCK 4 SS/ 5 tb0 6 tb1 7 tb2 8 tb3 9 Test coil 10 En_INT/ 11 VDDp 12 VDD ...

Page 4

... AS5050 Datasheet - Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in maximum rating conditions for extended periods may affect device reliability ...

Page 5

... AS5050 Datasheet - Electrical Characteristics 6.1 Operating Conditions Table 3. Operating Conditions Parameter DC supply voltage 1 Peripheral supply voltage Input pin voltage Ambient operating temperature (refer to External component 1. VDDp must not exceed VDD (protection diode between VDDp and VDD) 6 ...

Page 6

... Upon power-up, the AS5050 performs a full power-up sequence including one angle measurement. The completion of this cycle is indicated at the INT/ output pin and the angle value is stored in an internal register. Once this output is set, the AS5050 suspends to sleep mode. 7.1.1 Power Supply Filter Due to the sequential internal sampling of the Hall sensors, fluctuations on the analog power supply (pin#12: VDD) may cause additional jitter of the measured angle ...

Page 7

... Low Power Mode After completing the readout of an angle value, the device is in very low power condition. The AS5050 remains in sleep mode until it receives another angle reading request over the SPI interface. The average power consumption therefore depends on the interval, at which the external controller reads an angle over the SPI Interface ...

Page 8

... The transmitted data consists of 14-bit data, an Error-Flag and a Parity bit. When writing data to the chip, the Error-Flag is not applicable. The Parity is generated from the upper 15-bit and forms an even parity over the whole frame. The Error-Flag indicates that a failure occurred in a previous transmission. 7.2.1 Command Package Every command sent to the AS5050 is represented with the following layout. Table 6. Command Package Bit MSB ...

Page 9

... AS5050 Datasheet - 7.2.3 Write Data Package (Value Written to AS5050) The write frame is compatible to the read frame and contains two additional bits, the don’t care and parity flag. If the previous command was a write command a second package has to be transmitted. ...

Page 10

... For a single READ command two transmission sequences are necessary. The first package written to the AS5050 contains the READ command (MSB high) and the address the chip has to access, the second package transmitted to the AS5050 device can be any command the chip has to process next. The content of the desired register is available in the MISO register of the master device at the end of the second transmission cycle ...

Page 11

... AS5050 Datasheet - CLEAR ERROR FLAG Command. The CLEAR ERROR FLAG command is implemented as READ command. This command clears the ERROR FLAG which is contained in every READ frame. The READ data are 0x0000, which indicates a successful clear command. ...

Page 12

... Figure 8. SOFTWARE RESET Command MSB LSB SOFTWARE MOSI RESET command MISO Response -1 MSB LSB Transmission N In order to invoke a software reset on the AS5050 the following bit pattern has to be sent. Table 11. SOFTWARE RESET Command Bit MSB Table 12. Data Package ...

Page 13

... AS5050 Datasheet - NOP Command. The NOP command represents a dummy write to the AS5050. Figure 9. NOP Command MSB LSB MOSI NOP MISO Response -1 MSB LSB Transmission N The NOP command frame looks like follows. Table 13. NOP Command ...

Page 14

... The 16-bit SPI Interface enables read / write access to the register blocks and is compatible to a standard micro controller interface. The SPI module is active as soon as /SS pin is pulled low. The AS5050 then reads the digital value on the MOSI (master out slave in) input with every falling edge of SCK and writes on its MISO (master in slave out) output with the rising edge ...

Page 15

... AS5050 Datasheet - Figure 11. SPI Command / Response Data Flow MSB LSB MOSI Command 1 MISO 0x 00 MSB LSB Transmission 1 8.1.2 SPI Timing Figure 12. SPI Timing Diagram Input ) t L SCK ( Input ) t MISO MISO ( Output ) ...

Page 16

... Multiple Slave, n+3 Wire (Separate ChipSelect). Figure 14. Multiple Slave, n+3 Wire (Separate ChipSelect) MOSI MOSI MISO MISO AS5050 SCK UC SCK I SS1/ SS/ SS2/ Wire_ Mode 1 SS3/ MOSI MISO AS5050 SCK II SS/ Wire_ Mode 1 MOSI MISO AS5050 SCK III SS / Wire_ Mode 1 www.austriamicrosystems.com 0xFFFF 0xFFFF 0xFFFF 0xFFFF ...

Page 17

... UC MOSI MOSI MISO UC MISO AS5050 SCK II SS/ Wire_Mode 1 MOSI MISO AS5050 SCK III SS/ Wire_Mode 1 8.2 Placement of the Magnet Non-Linearity Error over Displacement. As shown in Figure 17, the recommended horizontal position of the magnet axis is over the diagonal center of the IC. Figure 16 shows a typical error curve at a vertical magnet distance of 1.0mm, measured with a NdFeB N35H magnet with 6mm diameter and 2 ...

Page 18

... AS5050 Datasheet - Figure 16. Integral Non-linearity Over Displacement of the Magnet 4 3.5 3 2.5 2 1.5 INL [°] 1 0.5 0 X-displacement [mm] www.austriamicrosystems.com Non-Linearity @ z=1mm 0.8 0.5 0.2 -0.1 Y-displacement [mm] -0.4 -0.7 -1.0 Revision 1.12 3.5-4 3-3.5 2.5-3 2-2.5 1.5-2 1-1.5 0.5-1 0-0 ...

Page 19

... Min Nom Max Notes e - 0.65 BSC - L 0.40 0.45 0.50 L1 0.10 Dx 1.85 2.00 2. 1.85 2.00 2. 0.323 0.383 0.443 Week Assembly plant identifier Revision 1.12 YYWWXZZ AS5050 e Notes: 1. Center of die to package edge 2. Center of die to package edge 3. Surface of die to package surface 4. Radius of Hall array X ZZ Assembly traceability code ...

Page 20

... AS5050 Datasheet - Revision History Revision Date 1.12 17 Feb, 2011 Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com Owner mub Revision 1.12 Description Latest draft ...

Page 21

... Ordering Information The devices are available as the standard products shown in Table 16. Ordering Information Ordering Code AS5050-EQFT 10-bit low power magnetic rotary encoder Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: Technical Support is available at http://www ...

Page 22

... AS5050 Datasheet - Copyrights Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. ...

Related keywords