e7804 Semtech Corporation, e7804 Datasheet - Page 11

• Manufacturer Part Number: e7804
• Description: 133 Mhz Quad Pin Electronics Driver And Window Comparator
• Manufacturer: Semtech Corporation

Figure 4 depicts two topologies to serially read and write
multiple E7804 devices on a single assembly.
4a daisy chains the serial I/O (SDOUT to SDIN) pins, and
the CLKIN and LOAD functions are common for all the
E7804s. This topology uses a minimum amount of
from the control logic. However, in order to read or write
the E7804’s an instruction string of 24 x N bits long needs
to be created, clocked all the way through the devices, and
a parallel LOAD signal asserted for all devices. NO_OP
instructions may be used for the devices that are not being
addressed.
Figure 4b shows a topology from the control logic that offers
rapid programming time and complete independence.
This topology relies on enough I/O signals being available
from the control logic. Notice that the CLKIN pins are
still all common because independence is allowed by the
individual LOAD signals to each E7804.
If it is determined that readback from the E7804s are
not necessary, the control logic can be further simplified.
Readback is not necessary for the operation of the
E7804. It is offered as a good diagnostic tool and possible
programming aid.
Read Serial Data
In order to readback data, an instruction is constructed
with the Read_Bit set to a logical ”” in the instruction
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
©
2007 Semtech Corp. / Rev. 7, 02/26/07
SDIN
CLKIN
LOAD
SDOUT
Bit 22 N
Figure 3. Serial Data Programming - Write Instruction
Instruction "N"
First
Bit 23 N
Bit 0 N+1
Bit 0 N
Instruction "N+1"
Instruction "N" Echo
Bit 1 N+1
Figure
I/O
Bit 22 N+1
Bit 22 N
Bit 23 N+1
stream and written to the E7804. The instruction stream
must be properly constructed for address and select bits
to insure that the proper register will be accessed for
readback. The data bits D0:D2 in this Read instruction
are Don’t_Care.
Refer to Figure 5 for a timing diagram of the readback
process and Figure 2 for a block diagram of how the
readback operation works. Once the LOAD signal is
asserted on the 24th high-going CLKIN edge to latch in
the READ instruction for a particular address, the internal
READ line will assert true and switch the SDOUT pin to
output data from the internal readback shift register. The
readback data will immediately start to output from the
SDOUT pin on the low-going edge of CLKIN. The readback
will continue for 24 bits.
The first 5 bits of data readback should be ignored. The
next 3 bits will be the requested register’s readback data.
Finally, the last 6 bits are logical zeros.
While clocking out the readback data, a new instruction can
be simultaneously clocked in at SDIN. At the conclusion
of the 24-bit readback, the SDOUT data will revert back to
echoing the SDIN data shifted by 24 clocks.
Bit 23 N

Bit 0 N+2
Bit 0 N+1
Bit 1 N+2
Bit 1 N+1
Instruction "N+1" Echo
Instruction "N+2"
Bit 21 N+1
Bit 22 N+2
Bit 22 N+1
Bit 23 N+2
Bit 23 N+1
Bit 0 N+2
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