hmc624lflp4e Hittite Microwave Corporation, hmc624lflp4e Datasheet - Page 4

• Manufacturer Part Number: hmc624lflp4e
• Description: 0.5 Db Lsb Gaas Mmic 6-bit Digital Attenuator, 60 - 500 Mhz
• Manufacturer: Hittite Microwave Corporation

Timing Diagram
Parallel Mode
(Direct Parallel Mode & Latched Parallel Mode)
Note: the parallel mode is enabled when P/s is set to low.
Direct Parallel Mode - the attenuation state is changed by the control voltage inputs D0-D5 directly. the Le (Latch
enable) must be at a logic high at all times to control the attenuator in this manner.
Latched Parallel Mode - the attenuation state is selected using the control voltage inputs D0-D5 and set while the
LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the
desired states the Le is pulsed. see timing diagram above for reference.
Power-Up States
If LE is set to logic LOW at power-up, the logic state of
PuP1 and PuP2 determines the power-up state of the
part per PuP truth table. If the Le is set to logic HIGH
at power-up, the logic state of D0-D5 determines the
power-up state of the part per truth table. the attenu-
ator latches in the desired power-up state approxi-
mately 200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, rF inputs. the relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
Bias Voltage Table
Control Voltage Table
For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824
state
High
Low
Vdd (V)
3
5
0 to 0.5V @ <1 µA
Phone: [phone]
2 to 3V @ <1 µA
Vdd = +3V
(Latched Parallel Mode)
Application Support: Phone: [phone] or [e-mail]
Idd (typ.) (mA)
0 to 0.8V @ <1 µA
2 to 5V @ <1 µA
v00.0511
0.12
0.15
Vdd = +5V
Fax: [phone]
DIGITAL ATTENUATOR, 60 - 500 MHz
PUP Truth Table
note: the logic state of D0 - D5 determines the power-
up state per truth table shown below when Le is high
at power-up.
Truth Table
Parameter
Min. serial period, t
Control set-up time, t
Control hold-time, t
Le setup-time, t
Min. Le pulse width, t
Min Le pulse spacing, t
serial clock hold-time from Le, t
Hold time, t
Latch Enable Minimum Width, t
setup time, t
Any combination of the above states will provide an attenuation
equal to the sum of the bits selected.
High
High
High
High
High
High
Low
Low
D5
Order On-line at www.hittite.com
Le
0
0
0
0
1
0.5 dB LSB GaAs MMIC 6-BIT
High
High
High
High
High
High
Low
Low
D4
PH.
Ps
PuP1
Control Voltage Input
X
0
1
0
1
Ln
High
High
High
High
High
High
sCK
Low
Low
CH
D3
Cs
LEW
HMC624LFLP4E
Les
PuP2
0
0
1
1
X
High
High
High
High
High
High
Low
Low
D2
Len
CKn
High
High
High
High
High
High
Low
Low
typ.
100 ns
20 ns
20 ns
10 ns
10 ns
630 ns
10 ns
0 ns
10 ns
2 ns
D1
relative Attenuation
Insertion Loss
0 to -31.5 dB
High
High
High
High
High
High
Low
Low
D0
-31.5
-24
-16
reference
Insertion
-31.5 dB
-0.5 dB
-16 dB
-2 dB
-4 dB
-8 dB
-1 dB
Loss
0 dB
8 - 4
8