lc01707plf Sanyo Semiconductor Corporation, lc01707plf Datasheet
lc01707plf
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lc01707plf Summary of contents
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... Ordering number : ENA1928 LC01707PLF Overview LC01707PLF is a vehicle-mounted FM multiple tuner IC with FM-FE, IF, IF-Filter, PLL, FM-DEMO and LPF incorporated multiple tuner can be developed with this one chip. It makes up a small-sized FM multiple tuners which can be mounted on PND. Functions • the FM tuner IC exclusively for the FM multiple. ...
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... TOP VIEW SIDE VIEW 6 0.16 SIDE VIEW SANYO : VQFN44K(6.0X6.0) LC01707PLF Conditions Conditions 22.5kHz dev, fm=1kHz, S/N=30dB input level 7.5kHz dev, fm=76kHz, S/N=10dB input level *1 22.5kHz dev, fm=1kHz 7.5kHz dev, fm=76kHz *1 22.5kHz dev, fm=1kHz 75.0kHz dev, fm=1kHz AM 30% mod 22 ...
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... This IC uses the signal of FM band frequency (VCO divided into 1/4) which leaks into ANT pin. If the VCO leakage affects the performance of the system, make sure to connect an isolator on ANT pin path. Component L1/L2 Local OSC coil L3 Differential input coil X1 Crystal LC01707PLF Freq.Count - LIM DEMO + N_AGC IF Complex ...
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... S-meter output Supply pin for IF 36 LPFO O Demodulation output (after band limitation) 37 DEMOO O Demodulation output 38 LPFI I Demodulation signal input pin 39 DEMOC O Capacitance connecting pin for demodulation detection GND P GND pin LC01707PLF Function st Mixer st Mixer No.A1928-4/18 ...
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... No connection GND pin 1st mixer for the PLL charge pump capacitor connection pin Supply pin for the 1 mixer Supply pin for local oscillator. LC01707PLF mixer Equivalent circuit ...
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... PLL_logic GND pin. 25 XTAL Crystal oscillator connection pin (clock input pin Station detector pin. 30 INT Test monitor pin connection connection connection. LC01707PLF Equivalent circuit 20pF 10pF Pin13 5pF V DD Continued on next page ...
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... PLL_logic supply voltage pin. S-meter output. 34 SMETER supply voltage pin 36 LPFO Demodulator output (After band limit). 37 DEMOO Demodulator output. 38 LPFI Demodulator signal input pin. LC01707PLF Equivalent circuit ...
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... Continued from preceding page. Pin No. Pin name Function 39 DEMOC Capacitor connection pin for demodulator detection connection connection connection connection. 44 GND GND pin. LC01707PLF Equivalent circuit (Pin_3 (Pin_8 (Pin_12 (Pin_17 (Pin_24) No.A1928-8/18 ...
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... SDA D6 MSB S SCL START or repeated START condition LC01707PLF 2 C-bus that consists of two bus lines of a serial data line (SDA) and a serial clock C Description ACK signal from slave D0 D1 Byte complate, Clock line held low while interrupt within slave interrrupts are serviced ...
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... CPU in software. *These signal timings restore the communication after its interruption. The register setting is never reset. *Software reset command is incompatible with I SDA SCL 1 S START condition LC01707PLF Release the SDA line(HIGH) ACK(master is transmitter ACK:acknowledgement NACK:not acknowledgement 2 C-bus format ...
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... Low level input voltage High level output voltage (open drain) Low level output voltage (open drain) *2: Output impedance of open drain becomes high at the high level output voltage. Output voltage equals (voltage = since drain is pulled LC01707PLF ...
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... Since the total number of internal register is 34, 2-bit data set on the MSB side becomes invalid. 64 addresses are accepted 6 bits are used, but only 34 registers are used. MSB Invakid address 3) Register data Each register data consists of eight bits MSB LC01707PLF LSB 0 1/0 R/W 0 LSB Valid address ...
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... From master to slave 2) Individual registers data reading SDA START condition Slave address Repeated Slave address START condition From master to slave LC01707PLF Write Invalid address ACK P 1/0 1/0 0 1/0 ACK STOP condition From slave to master Invalid address ...
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... DBPFO[6] 5 DBPFO[5] 4 DBPFO[4] 3 DBPFO[3] 2 DBPFO[2] 1 DBPFO[1] 0 DBPFO[0] LC01707PLF : Unused BIT Function Bit operation 0:DRS0 1:DRS1 2:DRS2 3:DRS3 4:DRS4 5:DRS5 6:DRS6 7:DRS7 0:15.6mVp-p 1:31.3mVp-p 4:78.1mVp-p 5:93.8mVp-p 8:140.6mVp-p 9:156.3mVp-p 10:171.9mVp-p 11:187.5mVp-p 12:203.1mVp-p 13:218.8mVp-p 14:234.4mVp-p 15:250mVp-p 1:Normal 0:Twice 1:Number of comparing 6 0:Munber of comparing 3 0:100kHz 1:50kHz 2:50kHz 3:25kHz ...
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... Local oscillator capacitor bank setting (low 8 bits) 6 DCBANK_L[6] 5 DCBANK_L[5] 4 DCBANK_L[4] 3 DCBANK_L[3] 2 DCBANK_L[2] 1 DCBANK_L[1] 0 DCBANK_L[0] LC01707PLF : Unused BIT Function 1:Normal 0:Twice 1:lower 0:upper 0:0.1mA 1:0.2mA 2:0.3mA 3:0.4mA 4:0.5mA 5:0.6mA 6:0.7mA 7:0.8mA 8:0.9mA A:1mA E: unused F: unused st IF frequency channel × step frequency) Read/ Binary Bit operation Write ...
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... IMRSSI[3] Reset detection circuit 2 IMRSSI[2] 1 IMRSSI[1] 0 IMRSSI[0] LC01707PLF : Unused BIT Function Bit operation 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 0:unused 1:IF frequency 2:prescaler frequency 3:freacaler frequency 4:f0 detection oscillation frequency 5:f0 detection oscillation frequency 6:unused 7:IF frequency 1:ON (frequency counter start) Charge to 0 automatically 0:4ms 1:8ms 2:32ms 3:64ms 1:LOCK 0:UNLOCK 0:less than 0 ...
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... F0_H[2] 1 F0_H[1] 0 F0_H[0] 1Fh DOUTSEL Register for TEST 1 DCNTEST Register for TEST 0 DOUTTEST Register for TEST LC01707PLF : Unused BIT Function Bit operation Detection range can be changed by setting to DNGA (02h) Read/ Binary Hex Write value value h’** R ...
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... This catalog provides information as of August, 2011. Specifications and information herein are subject to change without notice. LC01707PLF Function Bit operation 1:cap bank control value 0:I 1:correcting process after sequential comparison ...