kbc1100 Standard Microsystems Corp., kbc1100 Datasheet

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kbc1100

Manufacturer Part Number
kbc1100
Description
Mobile Kbc With Super I/o, Sfi, Adc And Dac With Smsc Sentinelalert Corporation
Manufacturer
Standard Microsystems Corp.
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
kbc1100L-PU
Manufacturer:
SMSC
Quantity:
846
PRODUCT FEATURES
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SMSC KBC1100
3.3V Operation with 5V Tolerant Buffers
ACPI 1.0b/2.0 and PC99a/PC2001 Compliant
LPC Interface with Clock Run Support
LPC/Firmware Hub Host Flash Interface
Serial Peripheral Interface (SPI)
8 MByte Shared FlashROM Interface (SFI)
Host Flash Address Redirection for Recovery
Serial Flash Programming Interface
Two Power Planes
3-Port ACPI Embedded Controller Interface
— Serial IRQ Interface Compatible with Serialized
— 15 Direct IRQs
— Three 8-Bit DMA Channels
— ACPI SCI Interface
— nSMI
— Shadowed write only registers
— Single Byte FWH Memory Read and FWH
— FWH ID Support
— 16MB FWH Flash and Register Addressing,
— Single Byte LPC Memory Read and LPC Memory
— 3-pin Full Duplex serial communication interface.
— Dual Ported Controller with Keeper Circuit
— 8051/Host CPU Hardware Arbitrated Interface
— 0.5 - 8MB - Host System BIOS & 8051 Keyboard
— 8051 64KB Code Space Accessible as Separate
— Low-Power Flash Access Modes
— 8051-Programmable Flash Access Protection
— Low Standby Current in Sleep Mode
— Intelligent Auto Power Management for Super I/O
— Main powered blocks power supplied by standby
IRQ Support for PCI Systems
Memory Write Support
128K Legacy BIOS Addressing
Write Support
32KB Pages in Flash
power plane and controlled by power
management signals
– Read/Write/No-Access Protection
– Variable Bank Sizes
PRODUCT PREVIEW
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Configuration Register Set
High-Performance Embedded 8051 Keyboard and
Advanced Infrared Communications Controller (IRCC
— Compatible with ISA Plug-and-Play Standard
— Four Pin Selectable Addressing Options
— 8051-Programmable Base Address
System Controller
— Provides System Power Management
— System Watch Dog Timer (WDT)
— 8042 Style Host Interface Relocatable to 480
— Supports Interrupt and Polling Access
— Interrupt Accelerator
— 512 Bytes Data RAM
— 2 Kilobytes Scratch ROM/RAM
— On-Chip Memory-Mapped Control Registers
— Up to 18x8 Keyboard Scan Matrix
— Two 16 Bit Timer/Counters
— Eleven 8051 Interrupt Sources
— Thirty-Two 8-Bit, Host/8051 Mailbox Registers
— Thirty-six Maskable Hardware Wake-Up Events
— Fast GATEA20
— Fast CPU_RESET
— Multiple Clock Sources and Operating
— IDLE and SLEEP Modes
— Low Power Fail-Safe Ring Oscillator ±10%
— Hibernation Timer with programmable wake-up
— 8051-Driven 16550A UART
— Power-Fail Status Register
2.0)
— IrDA V1.2 (4Mbps), HPSIR, ASKIR, Consumer IR
— Two IR Ports
— Relocatable Base I/O Address
Mobile KBC with Super
I/O, SFI, ADC and DAC
with SMSC
SentinelAlert!
KBC1100
(Version 1.0a)
Different Base I/O Addresses
Frequencies up to 32MHz
Accuracy
from 0.5ms to 128 minutes
Support
– 16-Byte Send/Receive FIFOs
– External Baud Clock Option
TM
Revision 0.8 (10-19-05)
Data Brief

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kbc1100 Summary of contents

Page 1

... Intelligent Auto Power Management for Super I/O — Main powered blocks power supplied by standby power plane and controlled by power management signals 3-Port ACPI Embedded Controller Interface I SMSC KBC1100 KBC1100 Mobile KBC with Super I/O, SFI, ADC and DAC with SMSC SentinelAlert! Configuration Register Set I — ...

Page 2

... Base I/O Address, 15 IRQ Options and 3 DMA Options — CIR supports NEC and RC5 framing — CIR supports RC6 framing under Philips license (p/n KBC1100P only) — 8051 access to RC6, RC5, and NEC received data — 8051/Host wakeup from specific RC5 and NEC ...

Page 3

... Mobile KBC with Super I/O, SFI, ADC and DAC with SMSC SentinelAlert! ORDER NUMBER(S): KBC1100-RD FOR 176 PIN, TQFP PACKAGE; KBC1100-RT FOR 176 PIN TQFP PACKAGE (GREEN, LEAD-FREE) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2005 SMSC or its subsidiaries. All rights reserved. ...

Page 4

... VCC1 power on reset for the KBC1100. The KBC1100 also outputs VCC1RST# which can be used to reset the Flash memory on the Shared Flash Interface (SFI). A block diagram of the KBC1100 including the distribution of the supply planes is shown below in Figure 1 on page 5 ...

Page 5

... Figure 1 KBC1100 Block Diagram 5 ...

Page 6

... SEATING PLANE A1 ccc C MAX 1.60 0.15 1.45 22.20 20.20 0.20 0.75 0.23 0.08 6 PRODUCT PREVIEW TM 0.25 0°-7° GAUGE PLANE DETAIL "A" (SCALE: 2/1) 3-D VIEW REMARK Overall Package Height Standoff Body Thickness X/Y Span X/Y Body Size Lead Foot Thickness Lead Foot Length Lead Length Lead Pitch Lead Width Coplanarity SMSC KBC1100 ...

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