mt90226ag ETC-unknow, mt90226ag Datasheet
mt90226ag
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mt90226ag Summary of contents
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... TX Tx Utopia FIFo Processor I/F Figure 1 - MT90225/226 Functional Block Diagram 16/8 Port TC PHY Device DS5664 Ordering Information MT90225AG MT90226AG - and UNI • ATM framing using cell delineation • HEC (header error control) verification & generation, error detection, and idle/unassigned cell filtering • ...
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Applications Provides cost effective solutions to implement TC (Transmission Convergence) functions over T1, E1 DSL transport facilities in broadband access networks. Typical applications are for trunking or subscriber access in: • Integrated multi-service access platforms • Access multiplexers ...
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Data Sheet 1.0 Device Architecture ......................................................................................................... 22 1.1 MT90225/6 Main Functions ...................................................................................................................... 22 2.0 The ATM Transmit Path................................................................................................... 23 2.1 Cell In Control ........................................................................................................................................... 23 2.2 The ATM Transmission Convergence ...................................................................................................... 24 2.2.1 TX Cell RAM and TX Link FIFO ...
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MT90225/226 6.2.1 IRQ Master Status and IRQ Master Enable Registers .................................................................... 45 6.2.2 IRQ Link Status and IRQ Link Enable Registers ............................................................................. 45 6.2.3 IRQ Link TC Overflow Status Registers .......................................................................................... 46 6.3 Microprocessor Interface Block................................................................................................................. 46 6.3.1 Access to ...
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Data Sheet Figure 1 - MT90225/226 Functional Block Diagram ................................................................................................1 Figure 2 - MT90226 Pinout (Bottom View) ..............................................................................................................9 Figure 3 - MT90225 Pinout (Bottom View) ........................................................................................................... 10 Figure 4 - MT90225/226 Functional Block Diagram -Transmitter ........................................................................ 24 Figure 5 - ...
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Zarlink Semiconductor Inc. Data Sheet ...
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Data Sheet Table 1 - Cell Acquisition Time..............................................................................................................................27 Table 2 - Register Summary .................................................................................................................................47 Table 3 - UTOPIA Output Link Address Registers ................................................................................................48 Table 4 - UTOPIA Output Link PHY Enable Registers..........................................................................................48 Table 5 - UTOPIA Output Control Register ...........................................................................................................49 ...
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Zarlink Semiconductor Inc. Data Sheet ...
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Data Sheet Pin Diagram - MT90226 The MT90226 uses a 384 pin PBGA with a 1.0mm ball pitch DSTi[4] NC VDD5 DSTi[2] NC RXSYN Ci[ VSS RXSYN NC RXCKi NC ...
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Pin Diagram - MT90225 The MT90225 uses a 384 pin PBGA with a 1.0mm ball pitch DSTi[4] RXCKi VDD5 DSTi[2] RXSYN RXSYN [3] Ci[1] Ci[ VSS RXSYN DSTi[3] RXCKi DSTi[1] ...
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Data Sheet MT90226 Pin Description Pin # Name I/O ATM Input Port Signals (UTOPIA Transmit Interface) U2,U1,T4,T2, UTxData I T1,R3,R4,R2, [15:0] R1,P3,P1,N1, N2,N3,M2,M4 U3 UTxPar I V1 UTxSOC I V4 UTxClk I V3 UTxEnb I V2 UTxClav O UTOPIA Transmit ...
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MT90226 Pin Description (continued) Pin # Name I/O J3 URxClav O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY L1, URxAddr I L2, [4:0] L4, L3, K1 AE8,AD8,AF7, up_d I/O Processor Data Bus. Data Bus to ...
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Data Sheet MT90226 Pin Description (continued) Pin # Name I/O DSTi I M26 [14] L24 [12] J23 [10] G25 [8] E26 [6] A25 [4] A22 [2] B20 [0] TXCKio I/O TDM Interface Transmit Clock. This pin is an input or ...
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MT90226 Pin Description (continued) Pin # Name I/O AA3,AA4, REFCK I AA1,Y3 [3:0] AC1 Clk I C19 LatchClk I A4 Reset I D7 TCK I A5 TMS I B6 TDI I C6 TDO O JTAG Test Data Output. Note: TDO ...
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Data Sheet MT90226 Pin Description (continued) Pin # Name I/O AB23,AC4, VSS S Ground. AC5,AC23, AD3,AD24, AE2,AE25,B2, B25,C3,C24, D4,D5,D23,E4, L11,L12,L13, L14,L15,L16, M11,M12,M13, M14,M15,M16, N11,N12,N13, N14,N15,N16, P11,P12,P13,P 14,P15,P16, R11,R12,R13, R14,R15,R16, T11,T12,T13, T14,T15,T16 IC I AC16,AE16, AF16,AC15, AE15,AF15, AD14,AE14 AF13, AF14 Description ...
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MT90226 Pin Description (continued) Pin # Name I/O B1,J2,M1,Y1 AA2,AC2,AD2, AE1,AC3,AF4, AC8,AE17, AC20,AD21, AF22,AF23, AD22,AE23, AF24,AE24, AF25,AD23, AE26,R24, L23,E25,C25, B26,D24,C15, A6,A3,C4, B3,A2 P24, T23, V24,Y26, AB26, AC24, AE20,AC18 P26, M24, K24, H23, F25, C26, B23, B21 N26, L26, ...
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Data Sheet MT90225 Pin Description Pin # Name I/O ATM Input Port Signals (UTOPIA Transmit Interface) U2,U1,T4,T2, UTxData I T1,R3,R4,R2, [15:0] R1,P3,P1,N1, N2,N3,M2,M4 U3 UTxPar I V1 UTxSOC I V4 UTxClk I V3 UTxEnb I V2 UTxClav O UTOPIA Transmit ...
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MT90225 Pin Description (continued) Pin # Name I/O J3 URxClav O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY L1, L2, L4, L3, URxAddr I K1 [4:0] AE8,AD8,AF7, up_d I/O Processor Data Bus. Data Bus to ...
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Data Sheet MT90225 Pin Description (continued) Pin # Name I/O P26,M26,M24, DSTi I L24,K24,J23, [15:0] H23,G25,F25, E26,C26,A25, B23,A22,B21, B20 R26,T26,T24, TXCKio I/O TDM Interface Transmit Clock 15-0. This pin is an input or an output as U24,V23,W24, [15:0] Y25,AA26, AB25,AC25, ...
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MT90225 Pin Description (continued) Pin # Name I/O C19 LatchClk I A4 Reset I D7 TCK I A5 TMS I B6 TDI I C6 TDO O JTAG Test Data Output. Note: TDO is tristated by TRST pin. B5 TRST I ...
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Data Sheet MT90225 Pin Description (continued) Pin # Name I/O AB23,AC4, VSS S Ground. AC5,AC23, AD3,AD24, AE2,AE25,B2, B25,C3,C24, D4,D5,D23,E4, L11,L12,L13, L14,L15,L16, M11,M12,M13, M14,M15,M16, N11,N12,N13, N14,N15,N16, P11,P12,P13, P14,P15,P16, R11,R12,R13, R14,R15,R16, T11,T12,T13, T14,T15,T16 IC I AC16,AE16, AF16,AC15, AE15,AF15, AD14,AE14 AF13, AF14 B1,J2,M1,Y1, ...
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Device Architecture The MT90225/226 implements Transmission Convergence layer functions. The primary function of MT90225 transfer the cells from the UTOPIA Interface to a serial (TDM) port and from TDM ports to UTOPIA interface without any overhead. Up ...
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Data Sheet 2.0 The ATM Transmit Path The transmit path corresponds to a cell flow from the ATM Layer towards the PHY Layer. The ATM cell path on the transmit side starts at the UTOPIA Interface. Once ...
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UTOPIA L2 Interface ATM In and Cell_in_control Figure 4 - MT90225/226 Functional Block Diagram -Transmitter 2.2 The ATM Transmission Convergence The Transmit Convergence (TC) function integrates the circuitry to support ATM cell payload scrambling, HEC generation and the generation of ...
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Data Sheet 2.2.1 TX Cell RAM and TX Link FIFO Length The internal TX Cell RAM can hold up to 119 cells. A one cell space for predefined Idle Cell is reserved for MT90225/226 operation. The remaining 118 cells can ...
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The ATM Receive Path The receive path corresponds to the cell flow from the PHY (serial TDM) interfaces to the ATM UTOPIA Interface. The MT90225/226 provides cell delineation and optional cell filtering to discard Unassigned or Idle cells on ...
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Data Sheet When a valid HEC is found, the CD circuit locks on the cell boundary and enters the PRESYNC state. The PRESYNC state keeps checking the HEC to ensure that the previous indication was not false. False indications are ...
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After correction (when enabled), the resulting ATM cell is passed to the Rx Link UTOPIA FIFO single or multi bit error occurs, the state machine transitions to the ’detection’ state. When a cell with a good HEC is ...
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Data Sheet 4.0 Description of the TDM Interface The Transmit TDM blocks are independent of the Receive TDM blocks. The TX port of a framer can be connected to any of the MT90225/226 TX UTOPIA Input ports and the RX ...
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This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by the following settings. Data rate (bits 6: Multiplex mode (bits 4: Clock and Sync format (bit ...
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Data Sheet 4.1.3 Single mode -ST-BUS This is used for T1/E1 connection with ST-BUS, where data rate is 2.048 Mb/s, clock is 4.096 MHz and frame pulse is 8KHz. A standard ST-BUS mode is supported with 32 time slots in ...
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Wire-OR mode - 2 link grouping Two links in a pair are OR’ed together by using this mode. The links that are paired are pre-determined: link 0 is paired with link 1, link 2 is paired with link 3 ...
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Data Sheet 4.3.1 Multiplex mode - 2 link multiplexing In this mode, two links of 2.048 Mb/s are multiplexed onto a single link of 4.096 Mb/s. The links that are paired are pre-determined: link 0 is multiplexed with link 1, ...
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Non-framed mode Single mode, Wire-OR mode and Multiplexed mode are all dealing with framed data, that is, a frame pulse must be present to give both byte and frame alignment. However, MT90225/226 also support a non-framed mode where only ...
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Data Sheet 4.4.3 Non-framed mode - 10.0Mbps If a serial link of more than 5Mbps but less than 10.0Mbps data rate is required, this mode can be applied. For every four links in a group, three are disabled and the ...
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Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters Each serial TDM link has assigned S/P and P/S units. The P/S unit takes a byte from the cell RAM and converts serial bit stream. The ...
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Data Sheet 4.8 Clocking Options TXCK and TXSYNC can be either input or output signals. When TXCK and TXSYNC are inputs, they are generated by external circuitry. When TXCK and TXSYNC are outputs, TXCK source is software selectable and can ...
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Verification of the TXSYNC Period The TXSYNC signal is used to align the outgoing DSTo data to retrieve all the channels. When defined as input, the TXSYNC pulse can be present for each TDM frame (8Khz) ...
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Data Sheet 5.0 UTOPIA Interface Operation The MT90225/226 supports the UTOPIA L1 and L2 Mode bit wide bus 52MHz, with odd/even parity, for cell level handshake only. Each port can be assigned an address ...
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The ’10’ option is used to verify the HEC on the incoming cell and discard the cell if the HEC value is wrong. The bad HEC counter is incremented if a cell is discarded. • The ’11’ option is ...
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Data Sheet 5.5 UTOPIA Operation with Multiple PHY When more than one MT90225/226 is connected to a single ATM Layer device the single TxClav and RxClav scheme is used. Direct Status Indication and Multiplexed Status Polling schemes are not supported. ...
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Figure 13 shows the connection of one ATM Device with more than one MT90225/226. ATM Layer ATM Figure 13 - ATM Interface to Multiple MT90225/226 42 Physical Layer Txclk TxEnb* TxAddr TxClav TxData TxSOC MT90225/226 Rxclk RxEnb* RxAddr RxClav RxData ...
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Data Sheet 6.0 Support Blocks 6.1 Counter Block The MT90225/226 includes 144 24-bit counters to provide statistical information on the device’s operation. All the counters are cleared by a hardware reset. A maskable interrupt can be generated when the counter ...
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The IRQ enable bit of a counter is set, or reset, by selecting the counter and writing to the appropriate bit of the Counter Transfer Command (0x040F) register. The value’0x001010’ enables the counter IRQ and ’xxx00010’ disables (masks) it. 6.1.5 ...
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Data Sheet 6.2.1 IRQ Master Status and IRQ Master Enable Registers There is a IRQ Master Status (0x0455) register that reports interrupts generated by any event on any of the links. Each bit of this register corresponds to a link. ...
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IRQ Link TC Overflow Status Registers The IRQ Link TC Overflow Status Registers (0x0410 - 0x041F) report the overflow condition from any of the counters associated with the TX TDM link, the RX TDM link or the TX UTOPIA ...
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Data Sheet 7.0 Register Descriptions Throughout the following register descriptions, it should be noted that only the registers and register bits corresponding to available links are meaningful. Registers and register bits corresponding to unavailable links should be masked or otherwise ...
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Address Access (Hex) Type 0x0600 - 0x060F D 0x0610 - 0x061F D 0x0620 - 0x062F D 0x0630 D 0x0631 D 0x0632 D 0x0633 D 0x0634- 0x0635 D 0x0700 - 0x070F D 0x0710 - 0x071F D 0x0720 - 0x072F D 0x0730 ...
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Data Sheet Address (Hex): 0x0011 (1 reg) Direct access Reset Value (Bin): X000000000000000 Type 15 R Reserved. 14 R/W Reserved. Write 0 for normal operation. 13 R/W Reserved. Write 0 for normal operation. 12 R/W Reserved. Write 0 for normal ...
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Address (Hex): 0x0050 (1 reg) Direct access 1 register to enable the link’s input PHY address. Reset Value (Hex): 0000 Bit # Type 15 R/W Enable UTOPIA PHY address of link 15 enables the PHY port Address. 14 ...
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Data Sheet Address (Hex): 0x0052 (1 reg) Direct access 1 register for all the UTOPIA Input ports. Reset Value (Hex): 000X000000000000 Bit # Type 15:14 R Unused. Read all 0’ Reserved. 12 R/W Parity Bit. The incoming Parity ...
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Address (Hex): 0x0053 (1 reg) Direct access 1 register to contain information about parity errors on the Tx UTOPIA data bus. Reset Value (Hex): 0000 Bit # Type 13 R Reading this register indicates that the transfer ...
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Data Sheet Address (Hex): 0x00C0 - 0x00C7 (8 reg) Direct access 1 register per 2 links. Link 0 is paired with link 8, link 1 with link 9 and so on. Reset Value (Hex): 0C0C Bit # Type 15 R/W ...
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Address (Hex): 0x00C9 (1 reg) Direct access 1 register for all 16 cell delineation state machines Reset Value (Hex): 0067 Bit # Type 15:8 R Unused, Read all 0’s. 7:4 R/W DELTA parameter value for the Cell Delineation register. The ...
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Data Sheet Address (Hex): 0x00E6 (1 reg) Direct access 1 register for all links. Reset Value (Hex): 0000 Bit # Type indicates that the Cell Delineation State Machine (CD) for the link Synchronized ...
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Address (Hex): 0x0318 - 0x031F (8 reg) Direct access 1 register per 2 links, link 0 is paired with link 8, link1 with link 9 and so on. The high byte controls link 8-15 and low byte controls links 0-7 ...
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Data Sheet Address (Hex): 0x040E (1 reg) Direct access Reset Value (Hex): 0000 Bit # Type 15:4 R Unused. Read all 0’s. 3 R/W Set when the UTOPIA output clock is missing or too slow. This latched bit is cleared ...
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Address (Hex): 0x0410 - 0x041F (16 reg) Direct access 1 register per link. The RxClk and TxClk signals must be active for correct register operation Reset Value (Hex): 0000 Bit # Type 15:13 R Unused. Read all 0’s. 12 R/W ...
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Data Sheet Address (Hex): 0x0431 (1 reg) Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued Reset Value (Hex): 0000 Bit # Type 15:0 R/W A read accesses ...
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Address (Hex): 0x0434 (1 reg) Direct access 1 register to enable interrupts from the links in TC mode. The RxClk signal must be active for correct register operation Reset Value (Hex): 00 Bit # Type 15:0 R/W When set to ...
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Data Sheet Address (Hex): 0x0445 - 0x0454 (16 reg) Direct access 1 Enable register per link Status reg Reset Value (Hex): 0000 Bit # Type 15:12 R Unused. Read all 0’s. 11:0 R/W Each bit set to ’1’ will enable ...
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Address (Hex): 0x0600 - 0x060F (16 reg) Direct access 1 reg. per TX link. Reset Value (Hex): 0000 Bit # Type 7 R/W Link enable When 0, the TX port is in high impedance mode When 1, the TX port ...
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Data Sheet Address (Hex): 0x0620 - 0x062F (16 reg) Direct access Control time slot 31:16 Reset Value (Hex): 0000 Bit # Type 15:0 R/W Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not ...
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Address (Hex): 0x0632 (1 reg) Direct access 1 reg. for all 4 REFCK signals Reset Value (Hex): 0000 Bit # Type 15:4 R Unused. Read 0’ When 1: REFCK3 faulty 2 R When 1: REFCK2 faulty 1 R ...
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Data Sheet Address (Hex): 0x0700 - 0x070F (16 reg) Direct access 1 reg. per RX link Reset Value (Hex): 0000 Bit # Type 15:12 R Unused. Read 0’ Reserved. Write 0 for normal operation. 10 R/W Automatic ATM ...
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Address (Hex): 0x0710 - 0x071F (16 reg) Direct access Control time slot 15:0 Reset Value (Hex): 0000 Bit # Type 15:0 R/W Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in use, ...
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Data Sheet 8.0 Application Notes 8.1 Connecting the MT90225/226 to Various T1/E1/J1 Framers Many off-the-shelf T1/E1/J1 framers require the generation of a 1.544 MHz or 2.048 MHz transmit clock reference signal at an input pin. The MT9042 can generate both ...
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DSTi[0] RXCK[0] TXCK[0] RXSYNC[0] TXSYNC[0] DSTo[0] UTOPIA MT90225 LEVEL 2 DEVICE BUS DSTi[15] RXCK[15] TXCK[15] RXSYNC[15] TXSYNC[15] DSTo[15] Note: All MT9076B devices are configured in Line Sync. mode Figure 16 - MT90225 interfacing MT9076 ST-BUS mode with asynchronous links. (each ...
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Data Sheet MT90225 TXSYNCo[0] RXCKi[0] UTOPIA RXSYNC[0] BUS ATM LAYER TXSYNCo[1] BUS RXCKi[1] RXSYNC[1] PLLREF0-1 DSTo[15] TXCKi[15] TXSYNCo[15] RXCKi[15] REFCK0-3 RXSYNCi[15] Dejittered TX CLK (1.544 or 2.048 MHz) MT9042 Transmit Clock Dejittering Function Figure 17 - MT90225 interfacing MT9076 Generic ...
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MT90225 UTOPIA Level 2 BUS Note: The MT9072 is configured in IMA mode. (asynchronous links with independent Rx and Tx clocks) 70 TXCKio[0] TXSYNCio[0] DSTo[0] DSTi[0] RXSYNCi[0] RXCKi[0] TXCKio[15] TXSYNCio[15] DSTo[15] DSTi[15] RXSYNCi[15] RXCKi[15] Figure 18 - MT90225 interfacing MT9072 ...
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Data Sheet 9.0 AC/DC Characteristics Absolute Maximum Conditions* Parameter 1 Supply Voltage (2.5 volt core) Supply Voltage (3.3 volt core) Supply Voltage (5.0 volt I/O) 2 Voltage at Digital Inputs (VDD5 connected to 3.3V) Voltage at Digital Inputs (VDD5 connected ...
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DC Electrical Characteristics* - Characteristics 7 Output High Current (up_d[15:0], DSTo[15:0], TxSYNCio[15:0], TxCLK[15:0]) 8 Output High Current UTOPIA 9 Output High Current (all other Digital Outputs) 10 Output Low Voltage (Digital Outputs) 11 Output Low Current (up_d[15:0], up_irq, DSTo[15:0], TxSYNCio[15:0], ...
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Data Sheet AC Electrical Characteristics - Utopia Interface Transmit Timing ( 50 MHz) Multi-PHY operation with input loads of 10pF each (40 pF total) Signal name UTxClk UTxData[15:0], UTxSOC, UTxEnb, UTxAddr[4:0] UTxClav[0] Note 1: Greater than 50MHz ...
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AC Electrical Characteristics - Utopia Interface Transmit Timing ( 25MHz) Multi-PHY operation with input loads of 10pF each (80pF total) Signal name DIR UTxClk A->P UTxData[15:0], UTxSOC, A->P UTxEnb, UTxAddr[4:0], UTXPAR UTxClav[0] A<-P AC Electrical Characteristics - ...
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Data Sheet Clock Signal Input Setup To Clock Clock Signal tT11 Signal Going Low Impedance From Clock Clock Signal t OD Note1: The UTOPIA specification AC Characteristics are based on the timing specification for the receiver side of a signal. ...
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CPU Interface Timing The CPU Interface of the MT90225/226 supports both the Motorola and Intel timing modes. No Mode Select pin is required. With Motorola devices, the Motorola R/W-signal is connected to the UP_R/W pin and the UP_OE pin ...
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Data Sheet AC Electrical Characteristics - CPU Interface Motorola Timing - Read Cycle Characteristics 1 R/W set-up time to UP_CS falling edge 2 Data valid after UP_CS falling edge. 3 UP_AD or UP_R/W hold time after UP_CS rising edge 4 ...
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AC Electrical Characteristics - CPU Interface Intel Timing - Read Cycle Characteristics 1 R/W set-up time to UP_CS falling edge 2 Data valid after both UP_OE and UP_CS are low. 3 UP_AD or UP_R/W hold time after UP_OE rising edge ...
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Data Sheet AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle Characteristics 1 UP_R/W set-up time to UP_CS falling edge 2 Address and Data set up before rising edge of UP_CS 3 UP_AD and Data hold time after ...
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AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle Characteristics 1 UP_CS set-up time to UP_R/W falling edge 2 Address and Data set up before rising edge of UP_R/W 3 UP_AD, UP_CS and Data hold time after UP_R/W ...
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Data Sheet AC Electrical Characteristics - Frame Pulse and CLK Characteristic 1 Frame pulse width (ST-BUS, Generic) Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s 2 Frame Pulse Setup Time (ST-BUS or Generic) ...
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AC Electrical Characteristics - Serial Streams for ST-BUS and Generic Interface Characteristic Sti Set-up Time 1 Sti Hold Time 2 3 Sto Delay - Active to Active 4 STo delay - Active to High-Z 5 STo delay - High-Z to ...
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Data Sheet F0i (positive) F0i (negative) CLK (positive) CLK (negative) STi Bit 0, Last Ch (Note1) STo Bit 0, Last Ch (Note1) F0o (positive) F0o (negative) Note 1: 2Mb/s mode, last channel = ch 31, 4Mb/s mode, last channel = ...
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AC Electrical Characteristics - JTAG Port and RESET Pin Timing Parameter TCK period width TCK period width LOW TCK period width HIGH TDI setup time to TCK rising TDI hold time after TCK rising TMS setup time to TCK rising ...
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Data Sheet AC Electrical Characteristics - System Clock and Reset Parameter CLK period width CLK period width LOW CLK period width HIGH CLK rising CLK falling RESET pulse width ‡ Note : Typical figures are =3.3V, ...
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List of Abbreviations and Acronyms AAL ATM Adaptation Layer ATM Asynchronous Transfer Mode CBR Constant Bit Rate CDV Cell Delay Variation CPE Customer Premises Equipment CRC Cyclic Redundancy Check DSU Data Service Unit FE Far End HEC Header Error ...
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Data Sheet 11.0 ATM Glossary Asynchronous Transfer Mode Adaptation Layer (AAL) - Standardized protocols used to translate higher layer services from multiple applications into the size and format of an ATM cell. Individual protocols are indexed as per the examples ...
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Out of Cell Delineation (OCD) Anomaly - As specified in ITU-T Recommendation I.432(30), an OCD anomaly is reported when ALPHA consecutive cells with incorrect HEC are received. It ceases to be reported when DELTA consecutive cells with correct HEC are ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors ...