am79c989 Advanced Micro Devices, am79c989 Datasheet
am79c989
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am79c989 Summary of contents
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... QuEST device, such as extended distance operation altered. The Am79C989 device provides an Interrupt pin to in- dicate changes in the internal status of the device. The interrupt function reduces CPU polling of status regis- ters and allows fast response time to changes in phys- ical layer conditions ...
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... Carrier Detect Link/Auto Neg Link Detect State Machine 10BASE-T Transceiver 1 10BASE-T Transceiver 2 10BASE-T Transceiver 3 Collision Detect Attachment Unit Interface Register Block Management Interface Am79C989 Network Interface TXD0+ Line Driver with TXD0- Wave Shaping RXD0+ Line Receiver with Smart Squelch RXD0- REXT TXD1+ ...
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... QuEST 11 Am79C989 44 PLCC 12 13 Version 2 Am79C989 VDD 39 38 RXD3+ RXD3- 37 RXD2+ 36 RXD2 VSSRX RXD1 RXD1- RXD0+ 31 RXD0- 30 VDDTX 29 21173B-2 3 ...
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... MDIO LOGIC SYMBOL QuASI DDIO V DDTX( SSAUI V SSTX(2) V SSRX V SSIO MENDEC MENDEC MENDEC MENDEC AUI Management Interface Am79C989 TXD+ TXD- Twisted Pair Ports (4 Ports) RXD+ RXD- QINT/CI- PCI/CI+ DO+ DO- DI+ DI- 21173B 21173B-4 ...
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... PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus) Am79C971B PCnet™- FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus Am79C974 PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems Description Am79C989 5 ...
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... DEVICE NUMBER/DESCRIPTION Am79C989 Quad Ethernet Switching Transceiver (QuEST) Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C989 Valid Combinations ...
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... PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Interrupt Function 3.3 Volt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Shared Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Non-Implemented Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Auto-Negotiation Control Register (Reg Auto-Negotiation Status Register (Reg Auto-Negotiation Advertisement Register (Reg Auto-Negotiation Link Partner Ability Register (Reg Am79C989 7 ...
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... Auto-Negotiation Next Page Register (Reg 7 Error Mask Register (Reg 20 SYSTEM APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 Mbps Ethernet Switch ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC CHARACTERISTICS OVER OPERATING RANGES UNLESS OTHERWISE SPECIFIED KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Am79C989 ...
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... Multiplexed serial receive data I/O PHYAD 4 internal address input upon reset Multiplexed receive data valid enable I/O PHYAD 3 internal address input upon reset Input Multiplexed serial transmit data Input Multiplexed transmit enable Am79C989 Pin Name Pin No. Pin Name VDDTX 34 VSSRX TXD2- 35 RXD2- TXD2+ ...
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... TXD2 are the 10BASE-T differential data drivers for port 2. RXD2 10BASE-T Receive Data Port 2 Input RXD2 are the 10BASE-T differential data receivers for port 2. TXD3 10BASE-T Transmit Data Port 3 Output TXD3 are the 10BASE-T differential data drivers for port 3. Am79C989 Pin Description ...
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... Multiplexed Collision Output QCLSN indicates a collision condition on the network. QCLSN for all 4 ports is time-division multiplexed onto this signal and is sampled with respect to SCLK. The channel’s slot is synchronized to the rising edge of QRST/STRB. At the rising edge of reset, QCLSN is sampled to determine PHYAD 2. Am79C989 11 ...
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... There is a single ground pin that is used for analog 10BASE-T receive pins. The VSSRX pin must be con- nected to ground. VSSAUI Analog I/O Ground Power There is a single ground pin that is used for analog AUI circuitry. The VSSAUI pin must be connected to ground. Am79C989 ...
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... The Jabber timer provides a sim- ple method to protect the network from excessively long frames. When the Jabber condition is invoked, the Collision indication will be asserted if the Link Integrity state machine is in the pass state. Am79C989 (1% tolerance) resistor connected in 13 ...
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... Remote Fault and Next Page are also sup- ported. If the remote device does not support Auto- Negotiation, the algorithm defaults to the standard 10BASE-T algorithm. Am79C989 ...
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... AUI interface is selected for port 0, the 10BASE-T cir- cuit on that interface is disabled. If the 10BASE-T cir- cuit is disabled, the 10BASE-T circuit will terminate the transmission and reception of link pulses as well as frame data. The AUI port will use the Manchester en- coder/decoder circuitry of that port. Am79C989 15 ...
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... QRX_VALID, and QRX_DATA. When receive data trig- gers the squelch paths of either the 10BASE-T or AUI receiver, the QRX_CRS signal is asserted at the earli- est possible time. Receive Carrier Sense (QRX_CRS) signal is used for signaling real-time network activity to the external device connected to the QuEST device. Am79C989 ...
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... A2, are matched to an internal QuEST device address which acts as a chip selection function. Setting each of these three bits combination allows specific designation eight QuEST devices. The lower two bits of the PHYAD designate the channel number of the designated QuEST device. Am79C989 DATA D DDDDDDDDDDDDDDD 15 0 ...
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... Four registers are globally shared among all four ports: Registers 2 and 3 designate the Device ID, Register 16 is Interrupt Enable and Status, and Register 17 is Sum- mary Status. When accessing the shared registers, the lower two bits of the PHYAD address (bits A1 and A0) are ignored. Am79C989 PHYAD [0:1] /Port Register Name ...
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... Auto-Negotiation Control Register (Reg 0) The Auto-Negotiation Control Register (Reg 0) con- tains Read/Write (R/W), Read/Only (R/O), and Self- Clearing (SC) bits. This register is duplicated for each port. Description Am79C989 Register Name Auto Negotiation Control Auto Negotiation Status Auto Negotiation Address Auto Negotiation Link Partner Auto Negotiation Expansion ...
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... Jabber Condition detected; 1 Jabber Detect 0 = Jabber Condition not detected Extended Register Capability; Extended Register 0 Capability 0 = Not applicable Read/Only (R/O) bits or Clear on Read (COR) bits. This register is duplicated for each port. Description Am79C989 R/W 0 R/W 0 R/O 0 Read/ Default/ Write Reset R/O 0 R/O ...
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... Read/Write R/O R/O R/O basis. The purpose of this register is to advertise the technology ability to the link partner device. When this register is modified, Restart Auto-Negotiation (Reg 0, bit 9) must be set to advertise the change. Description Am79C989 Default/Reset Default/Reset (binary) (Hex) 0000 0000 0000 0000 0000 Default/Reset ...
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... The register is Read/Only (R/O). The bits rep- resent the received link code word. This register con- tains either the base page or the link partner's next pages. This register is duplicated for each port. Table 12. Base Page Format Description Table 13. Next Page Format Description Am79C989 Read/ Default/ Write Reset R/O 0 R/O ...
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... Read/Only (R/O) or Cleared on Read (COR). This register is duplicated for each port. Description Read/Write (R/W) or Read/Only (R/O) bits. On power- up the default value of 0x2001 represents a message page with the message code set to null. This register is duplicated for each port. Description Am79C989 Read/ Default/ Write Reset R/O 0 R/O ...
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... Register bit is cleared on Read Change in status of any of the above interrupts; Global Interrupt condition. Interrupt Register bit is Cleared on Read Read (COR) bits. This register is shared across all ports. Description Am79C989 Read/ Default/ Write Reset R/O 0 R/W 0 R/W 0 R/W ...
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... MAU Error 0 Port MAU Error on Port (R/O). The summary register allocates four bits per each port. Each port conveys: Link Status, Duplex Sta- tus, Auto-Negotiation Alert, and 10BASE-T MAU Error. Description Am79C989 Read/ Default/ Write Reset R/O 0 R/O 0 ...
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... When the port is configured for full duplex, heartbeat signal is automatically disabled Control Register contains Read/Write (R/W) or Read/ Only (R/O) bits. This register is duplicated for each port. Table 18. Control Register (Reg 18) Description Am79C989 Read/ Default/ Write Reset R/W 0 R/O 0 ...
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... Read/Only (R/O) bits error does occur and the Mask enable bit is set the Error bit in the Sum- mary Register (Reg 17) will not be asserted. This reg- ister is duplicated for each port. Table 19. Error Mask Register (Reg 20) Description Am79C989 Read/ Default/ Write Reset R/O ...
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... QRX_CRS TXD3+ 110 SCLK TXD3- QRST/STRB VDD RXD3+ 100 RXD3- QINT PCI/CI+ 40.2 or MDC 40.2 MDIO CI- DI+ 40.2 40.2 DI- DO+ DO- a special circuit (not shown) is needed for PCI. Optional , Am79C989 RJ45 Connector 1:1 1:1 RJ45 Connector 1:1 1:1 RJ45 Connector 1:1 1:1 RJ45 Connector 1:1 1:1 AUI Connector (Optional) 1:1 0. 10.1 F 1:1 0. 10.1 F 1:1 21173B-5 ...
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... 5.0 Volts DDIO 3.3 Volts DDIO 0<V < DDIO 0<V < DDIO V <V <V SSAUI <V <V SSAUI 80 80 80.4 (Note 80 80.4 Am79C989 , DDIO DD, DDTX ) . . . . . . . . . . . . . . +3 DDIO Min Max Unit - 0 0.5 V DDIO 0 -10 A -500 +500 A -500 +500 A 620 ...
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... MHz Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz (Note 1) Am79C989 Min Max Unit -35 +35 mV -275 -160 mV -2.5 +2 -3 -500 500 -3.0 V -1.5 ...
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... Must be Will be Steady Steady May Will be Change Changing from from May Will be Change Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State KS000010-PAL Am79C989 31 ...
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... Strobe Pulse Width of QRST/STRB. MSI9B Channel 0 Channel 1 Channel 2 8 Not defined Channel 3 Channel 0 Parameter Description Am79C989 Channel 3 Channel 0 Channel 1 Channel 1 Channel 2 Channel 3 21173B-6 Min Max 24.9975 25.0025 ...
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... MDIO valid from rising edge of MDC. MII7 18 t MDIO TRI-STATE® delay from rising edge of MDC. MII8 Write to Quest Device Read from Quest Device Parameter Description Am79C989 17 18 21173B-7 Min Max Unit 50 — 20 — 20 — 10 — ...
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... FLP2 23 Total Pulses in FLP Burst. 24 FLP Burst to FLP Burst Clock Pulses Clock Pulse Figure 4. Fast Link Pulse Timing Diagram Parameter Description Am79C989 D15 = 0 21173B-8 Min Max 80 120 55.5 69.5 111 139 ...
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... CI Pulse Width Maintain/Turn-Off Threshold. PWKCI End of Transmission Delimiter. DOETD 100 mV 80 Bit Times Figure 5. AUI Timing Diagram Parameter Description Am79C989 21173B-9 Min Max Unit 136 200 160 ns 275 ...
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... RXD High/Low Frequency Time-out. TP2 42 t TXD End of Transmission Delimiter. TP2 Squelch Post-Squelch Timeout Parameter Description Am79C989 VTHS+, VLTHS+ VTHS–, VLTHS– 42 21173B-10 Min Max Unit — 15 MHz 160 180 ns 250 375 ...
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... Product names used in this publication are for identification purposes only and may be trademarks of their respective companies .062 .083 .042 .056 .009 .015 .090 .120 .165 .180 SIDE VIEW Am79C989 .500 .590 REF .630 .013 .021 SEATING PLANE 16-038-SQ PL 044 DA78 6-28- ...