am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 63

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access
Port is provided for board-level continuity test and diag-
nostics. All digital input, output, and input/output pins
are tested. Analog pins, including the AUI differential
driver (DO ) and receivers (DI , CI ), and the crystal in-
put (XTAL1/XTAL2) pins, are tested. The T-MAU drivers
TXD , TXP , and receiver RXD are also tested.
The following is a brief summary of the IEEE 1149.1
compatible
PCnet-ISA
Boundary Scan Circuit
The boundary scan test circuit requires four extra pins
(TCK, TMS, TDI and TDO ), defined as the Test Access
Port (TAP). It includes a finite state machine (FSM), an
instruction register, a data register array, and a
power-on reset circuit. Internal pull-up resistors are pro-
vided for the TDI, TCK, and TMS pins. The TCK pin must
not be left unconnected. The boundary scan circuit re-
mains active during sleep.
TAP FSM
The TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power-up or RESET. An inde-
pendent power-on reset circuit is provided to ensure the
FSM is in the TEST_LOGIC_RESET state at power-up.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP and SET-
BYP) are provided to further ease board-level testing.
Instruction
SAMPLE
SETBYP
BYPASS
EXTEST
IDCODE
TRIBYP
Name
+
controller.
test
functions
External Test
ID Code Inspection
Sample Boundary
Force Tristate
Control Boundary to 1/0
Bypass Scan
implemented
Description
IEEE 1149.1 Supported Instruction Summary
P R E L I M I N A R Y
in
Am79C961
the
All unused instruction codes are reserved. See the table
below for a summary of supported instructions.
Instruction Register and Decoding Logic
After hardware or software RESET, the IDCODE in-
struction is always invoked. The decoding logic gives
signals to control the data flow in the DATA registers ac-
cording to the current instruction.
Boundary Scan Register (BSR)
Each BSR cell has two stages. A flip-flop and a latch are
used in the SERIAL SHIFT STAGE and the PARALLEL
OUTPUT STAGE, respectively.
There are four possible operational modes in the BSR
cell:
Other Data Registers
(1) BYPASS REG (1 BIT)
(2) DEV ID REG (32 bits)
Bits 31–28:
Bits 27–12:
Bits 11–1:
Bit 0:
Data Reg
Selected
ID REG
Bypass
Bypass
Bypass
BSR
BSR
1
2
3
4
Version
Part number (2260)
Manufacturer ID. The 11 bit
manufacturer ID code for AMD is
00000000001 according to JEDEC
Publication 106-A.
Always a logic 1
Capture
Shift
Update
System Function
Normal
Normal
Normal
Normal
Mode
Test
Test
Instruction
Code
0000
0001
0010
0011
0100
1111
AMD
1-537