am79c930 Advanced Micro Devices, am79c930 Datasheet - Page 47

• Manufacturer Part Number: am79c930
• Description: Pcnet-mobile Single-chip Wireless Lan Media Access Controller
• Manufacturer: Advanced Micro Devices

accesses to use the memory interface bus during the T1
and T2 cycles of the 80188 access. The Memory Ad-
dress Bus is internally shared between the 80188 core
and the BIU. This bus also attaches to the Transceiver
Attachment Unit as an input only.
Data values are delivered from the 80188 core to the
SRAM through the BIU and then to the Memory Data
Bus (signals MD[7:0]). This bus is shared by the BIU for
access to the SRAM and also attaches to the Trans-
ceiver Attachment Unit.
Flash Memory Management
The 80188 core accesses the Flash memory by assert-
ing its Upper Chip Select (80188 UCS) This signal
remains internal to the Am79C930 device. The internal
UCS signal is routed into the BIU, since the 80188 core
and the BIU must share the memory interface bus. The
BIU in turn produces the Memory Interface signal FCE
that may be attached to the CE input of a Flash memory
device external to the Am79C930 device.
An alternative mapping scheme allows some portion of
the Flash memory to be mapped into a portion of LCS
space. (Normally, Flash memory is mapped only to UCS
space.) Therefore, depending upon the mapping
scheme that is chosen, Flash memory may be visible
only in UCS space, or portions of Flash memory may be
visible in both LCS and UCS spaces. For mapping
details, see the section on MAC Firmware Resources .
Address values are delivered from the 80188 core to the
Flash memory through the BIU and then to the Memory
Address Bus (signals MA[16:0]). The Memory Address
Bus is shared between the 80188 core and the BIU. The
sharing uses a priority scheme where the requester al-
ways has higher priority than the current bus master.
This ensures that in the worst case the system interface
access will be delayed only by the length of a single
80188 access, and an 80188 access will be delayed at
most by the length of a single system interface access.
The requesting access is always held off by asserting
the local ready signal. The memory interface bus also
attaches to the TAI Unit. The TAI is a bus slave device; it
cannot act as a bus master.
Data values are delivered from the 80188 core to the
Flash memory through the BIU and then to the Memory
Data Bus (signals MD[7:0]). Up to 128K of Flash mem-
ory may be addressed by the 80188 core. Note that for
PCMCIA operation, the 1K–16 bytes of the upper 1K
locations may be used for the PCMCIA CIS, since these
locations are mapped to Attribute Memory space when
P R E L I M I N A R Y
Am79C930
the PCMCIA mode of operation has been selected. Note
that the uppermost 16 bytes of Flash space are used by
the 80188 core to fetch initial instructions following a
reset operation of the Am79C930 device. Therefore,
these 16 bytes cannot be used for PCMCIA CIS. Note
that both the 80188 core and the system interface
(through Common Memory mapping) have access to
the PCMCIA CIS storage area, even though these loca-
tions should be reserved for PCMCIA CIS use.
Transceiver Attachment Interface Unit
Management
The 80188 core communicates with the TAI Unit
through memory accesses that the 80188 core performs
on the Memory Interface bus through the BIU. TIR regis-
ters are mapped to 32 byte locations of the SRAM
space, thereby rendering those 32 bytes of SRAM as
inaccessible to the 80188 core. Command and status
information for the TAI is passed through the TIR regis-
ters. Network data is passed to/from the TAI FIFOs with
DMA cycles. The TAI uses DMA channels 0 and 1 of the
80188 core. DMA channel 0 is used by the RX FIFO and
DMA channel 1 is used by the TX FIFO. The 80188 core
must activate its LCS signal to access the TIR registers,
just as in the case of SRAM accesses. As a result, the
TAI register set overlaps a very small portion of the
SRAM space. The TAI may send interrupts to the 80188
core through the INT0 interrupt.
Bus Interface Unit Interaction
The 80188 core communicates with the driver software
through a shared area of SRAM. When either the driver
software or the 80188 core modifies this area of SRAM,
an interrupt is generated to notify the receiving subunit.
Most command and status information for the adapter
may be passed to the driver through the shared SRAM.
However, a few physical registers do exist in the BIU to
facilitate the exchange of some very high level com-
mands, such as RESET, HALT, POWERDOWN and
INTERRUPT. Each subunit (device driver and 80188
core) is allotted its own set of BIU registers. The device
driver has access to eight System Interface Registers
(SIR) that reside in the BIU. The 80188 core has access
to 16 MAC Interface Registers (MIR) that reside in the
BIU. Communication of high-level command and status
information between the two subunits is indirectly
accomplished, in that modification of bits in the SIR
space will affect bits in the MIR space and vice versa,
but the device driver has no direct access to the MIR
space and the 80188 core has no direct access to the
SIR space.
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