89hpes16t4bg2 Integrated Device Technology, 89hpes16t4bg2 Datasheet
89hpes16t4bg2
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89hpes16t4bg2 Summary of contents
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... Device Overview The 89HPES16T4BG2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES16T4BG2 is a 16-lane, 4- port Gen2 peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides connec- ...
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... IDT 89HPES16T4BG2 Data Sheet ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – ...
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... IDT 89HPES16T4BG2 Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES16T4BG2 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES16T4BG2 registers supports SMBus arbitration ...
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... IDT 89HPES16T4BG2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES16T4BG2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...
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... IDT 89HPES16T4BG2 Data Sheet Signal SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] © 2009 Integrated Device Technology, Inc Type Name/Description I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. ...
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... IDT 89HPES16T4BG2 Data Sheet Signal GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] Signal CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[2:0] © 2009 Integrated Device Technology, Inc Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6 ...
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... IDT 89HPES16T4BG2 Data Sheet Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal REFRES0 REFRES2 REFRES4 REFRES6 V CORE PEA DD V PEHA DD V PETA © 2009 Integrated Device Technology, Inc Type Name/Description I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller ...
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... IDT 89HPES16T4BG2 Data Sheet Pin Characteristics Note: Some input pads of the PES16T4BG2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...
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... IDT 89HPES16T4BG2 Data Sheet Function EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N SerDes Reference REFRES0 Resistors REFRES2 REFRES4 REFRES6 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. Schmitt Trigger Input (STI). © 2009 Integrated Device Technology, Inc ...
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... IDT 89HPES16T4BG2 Data Sheet Logic Diagram — PES16T4BG2 Reference Clocks Reference Clock Frequency Selection PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 4 PCI Express Switch SerDes Input Port 6 MSMBADDR[4:1] Master SMBus Interface ...
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... IDT 89HPES16T4BG2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter Description Refclk Input reference clock frequency range FREQ T Rising edge rate C-RISE T Falling edge rate C-FALL V Differential input high voltage ...
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... IDT 89HPES16T4BG2 Data Sheet Parameter T Maximum time to transition to a valid Idle after sending TX-IDLE-SET-TO-IDLE an Idle ordered set T Maximum time to transition from valid idle to diff data TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any 2 lanes TX-SKEW T Minimum Instantaneous Lone Pulse Width ...
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... IDT 89HPES16T4BG2 Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state ...
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... IDT 89HPES16T4BG2 Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PEA PCI Express Analog Power PEHA PCI Express Analog High Power DD V PETA PCI Express Transmitter Analog Voltage DD V Common ground SS 1 ...
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... IDT 89HPES16T4BG2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...
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... IDT 89HPES16T4BG2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output TX-DIFFp-p voltage V Low-Drive Differential Peak to TX-DIFFp-p-LOW ...
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... IDT 89HPES16T4BG2 Data Sheet I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak-to- RX-DIFFp-p peak) RL Receiver Differential Return Loss RX-DIFF RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance (DC) RX-DIFF- common mode impedance RX--DC Z Powered down input common RX-COMM-DC ...
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... IDT 89HPES16T4BG2 Data Sheet Package Pinout — 288-BGA Signal Pinout for PES16T4BG2 The following table lists the pin numbers and signal names for the PES16T4BG2 device. Pin Function Alt Pin A1 V B13 B14 I/O B15 CORE B16 DD A5 PE6RP03 ...
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... IDT 89HPES16T4BG2 Data Sheet Pin Function Alt Pin L1 V R21 R22 PEHA L19 V PEA T3 DD L20 L21 REFRES4 T19 L22 V T20 T21 SS M2 REFRES2 T22 PEA U2 DD M19 M20 V PEHA ...
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... IDT 89HPES16T4BG2 Data Sheet Pin Function Alt Pin R20 PE4TN01 W12 Alternate Signal Functions No Connection Pins © 2009 Integrated Device Technology, Inc Function Alt Pin V PEA AA6 Table 18 PES16T4BG2 288-pin Signal Pin-Out (Part Pin GPIO Alternate AA21 GPIO_00 P2RSTN ...
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... IDT 89HPES16T4BG2 Data Sheet Power Pins V Core A10 A13 A16 D18 D22 K22 N1 N22 T1 T22 V19 W5 AB4 AB7 AB10 AB13 AB16 © 2009 Integrated Device Technology, Inc V I/O V PEA A19 D8 C8 D11 C22 D13 D2 D16 H20 E19 ...
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... IDT 89HPES16T4BG2 Data Sheet Ground Pins © 2009 Integrated Device Technology, Inc D17 M21 A2 E2 M22 A11 F2 N20 A12 F4 P4 A22 F19 P19 B12 G22 P20 B14 H2 P21 B15 J2 R21 B17 J3 U4 B18 J4 U19 B19 J19 U21 B22 ...
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... IDT 89HPES16T4BG2 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE No Connection © 2009 Integrated Device Technology, Inc ...
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... IDT 89HPES16T4BG2 Data Sheet Signal Name PE0RN00 PE0RN01 PE0RN02 © 2009 Integrated Device Technology, Inc I/O Type Location I AB5 I AB8 I AB14 Table 23 89PES16T4BG2 Alphabetical Signal List (Part *Notice: The information in this document is subject to change without notice Signal Category PCI Express ...
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... IDT 89HPES16T4BG2 Data Sheet Signal Name PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 PE4RP02 © ...
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... IDT 89HPES16T4BG2 Data Sheet Signal Name PE4RP03 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PE6RN00 PE6RN01 PE6RN02 PE6RN03 PE6RP00 PE6RP01 PE6RP02 PE6RP03 PE6TN00 PE6TN01 PE6TN02 PE6TN03 PE6TP00 PE6TP01 PE6TP02 PE6TP03 PEREFCLKN0 PEREFCLKP0 PERSTN REFCLKM REFRES0 REFRES2 REFRES4 REFRES6 RSTHALT © 2009 Integrated Device Technology, Inc ...
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... IDT 89HPES16T4BG2 Data Sheet Signal Name SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 V CORE PEA PETA © 2009 Integrated Device Technology, Inc I/O Type Location I AA17 I Y18 I AA18 I/O, See Table 21 for a listing of power pins. ...
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... IDT 89HPES16T4BG2 Data Sheet PES16T4BG2 Pinout — Top View Core (Power I/O (Power) DD Vss (Ground) © 2009 Integrated Device Technology, Inc ...
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... IDT 89HPES16T4BG2 Data Sheet PES16T4BG2 Package Drawing — 288-Pin BX288/BXG288 © 2009 Integrated Device Technology, Inc *Notice: The information in this document is subject to change without notice July 1, 2009 ...
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... IDT 89HPES16T4BG2 Data Sheet PES16T4BG2 Package Drawing — Page Two © 2009 Integrated Device Technology, Inc *Notice: The information in this document is subject to change without notice July 1, 2009 ...
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... IDT 89HPES16T4BG2 Data Sheet Revision History July 1, 2009: Initial publication of Advance data sheet. © 2009 Integrated Device Technology, Inc *Notice: The information in this document is subject to change without notice July 1, 2009 ...
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... IDT 89HPES16T4BG2 Data Sheet Ordering Information NN A NNANA Product Operating Product Family Voltage Detail Valid Combinations 89H16T4BG2ZABX 288-ball SBGA package, Commercial Temperature 89H16T4BG2ZABXG 288-ball Green SBGA package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’ ...