89hpes12nt3 Integrated Device Technology, 89hpes12nt3 Datasheet

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89hpes12nt3

Manufacturer Part Number
89hpes12nt3
Description
12-lane, 3-port Pcie Inter-domain Switch
Manufacturer
Integrated Device Technology
Datasheet

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Device Overview
PCI Express® switching solutions offering the next-generation I/O inter-
connect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip
that performs PCI Express Base switching with a feature set optimized
for high performance applications such as servers, storage, and commu-
nications/networking. It provides high-performance I/O connectivity and
switching functions between a PCIe® upstream port, a transparent
downstream port, and a non-transparent downstream port.
can be used standalone or as a chipset with IDT PCIe System Intercon-
nect Switches in multi-host and intelligent I/O applications such as
communications, storage, and blade servers where inter-domain
communication is required.
Features
Block Diagram
© 2007 Integrated Device Technology, Inc.
The 89HPES12NT3 is a member of the IDT PRECISE™ family of
With non-transparent bridging (NTB) functionality, the PES12NT3
– Twelve PCI Express lanes (2.5Gbps), three switch ports
– Delivers 48 Gbps (6 GBps) of aggregate switching capacity
– Low latency cut-through switch architecture
– Support for Max Payload size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– PCI Express Base specification Revision 1.0a compliant
High Performance PCI Express Switch
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
...
®
x4 Upstream Port and Two x4 Downstream Ports
SerDes
Logical
Layer
Phy
12-lane 3-Port Non-Transparent
PCI Express® Switch
*Notice: The information in this document is subject to change without notice
Route Table
SerDes
Logical
Layer
Phy
12 PCI Express Lanes
Figure 1 Internal Block Diagram
Multiplexer / Demultiplexer
3-Port Switch Core
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
1 of 29
...
SerDes
Logical
Arbitration
Layer
Phy
– Port arbitration schemes utilizing round robin
– Supports automatic per port link width negotiation (x4, x2, or
– Static lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy soft-
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
– Crosslink support on NTB port
– Four mapping windows supported
– Interprocessor communication
– Allows up to sixteen masters to communicate through the non-
– No limit on the number of supported outstanding transactions
– Completely symmetric non-transparent bridge operation
– Supports direct connection to a transparent or non-transparent
Flexible Architecture with Numerous Configuration Options
Non-Transparent Port
Port
x1)
ware
• Each may be configured as a 32-bit memory or I/O window
• May be paired to form a 64-bit memory window
• Thirty-two inbound and outbound doorbells
• Four inbound and outbound message registers
• Two shared scratchpad registers
transparent port
through the non-transparent bridge
allows similar/same configuration software to be run
port of another switch
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
Scheduler
Preliminary Information*
...
Inc.
SerDes
89HPES12NT3
Transparent
Logical
Layer
Phy
Bridge
Non-
Data Sheet
April 11, 2007
DSC 6929

Related parts for 89hpes12nt3

89hpes12nt3 Summary of contents

Page 1

... Device Overview The 89HPES12NT3 is a member of the IDT PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O inter- connect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and commu- nications/networking. It provides high-performance I/O connectivity and switching functions between a PCIe® ...

Page 2

... IDT 89HPES12NT3 Data Sheet Highly Integrated Solution ◆ – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twelve 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – ...

Page 3

... IDT 89HPES12NT3 Data Sheet PCIe System Interconnect Switch To Server CPU CPU PES12NT3 PES12NT3 PCIe System Interconnect Switch Embedded Embedded CPU CPU FC SATA / SAS Figure 2 PCIe System Interconnect Architecture Block Diagram Controller 1 CPU Cache Maint. & PES12N3 Possible Data Flow x4 PCIe x4 PCIe ...

Page 4

... IDT 89HPES12NT3 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12NT3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...

Page 5

... IDT 89HPES12NT3 Data Sheet Signal SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] Type Name/Description I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus ...

Page 6

... IDT 89HPES12NT3 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PENTBRSTN PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI Type Name/Description I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. I Common Clock Upstream. When the CCLKUS pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port ...

Page 7

... IDT 89HPES12NT3 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated ...

Page 8

... IDT 89HPES12NT3 Data Sheet Pin Characteristics Note: Some input pads of the PES12NT3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...

Page 9

... IDT 89HPES12NT3 Data Sheet Function System Pins JTAG Pin Name Type Buffer CCLKDS I LVTTL CCLKUS I MSMBSMODE I PENTBRSTN I PERSTN I RSTHALT I SWMODE[3:0] I JTAG_TCK I LVTTL JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_TRST_N I Table 7 Pin Characteristics (Part I/O Internal Notes Type Resistor Input pull-up pull-up pull-down ...

Page 10

... IDT 89HPES12NT3 Data Sheet Logic Diagram — PES12NT3 Reference Clock PCI Express Switch SerDes Input Port A PCI Express Switch SerDes Input Port B PCI Express Switch SerDes Input Port C Master SMBus Interface SSMBADDR[5,3:1] Slave SMBus Interface System Pins 2 PEREFCLKP 2 PEREFCLKN REFCLKM PEALREV ...

Page 11

... IDT 89HPES12NT3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing ...

Page 12

... IDT 89HPES12NT3 Data Sheet Parameter T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ENTER TIME T Lane to lane input skew RX-SKEW 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a ...

Page 13

... IDT 89HPES12NT3 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power PCI Express Serial Data Transmit ...

Page 14

... IDT 89HPES12NT3 Data Sheet Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES12NT3, the power-up sequence must be as follows I/O — 3. Core, V PE, V APE — 1. — ...

Page 15

... IDT 89HPES12NT3 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V Differential peak-to-peak output voltage TX-DIFFp-p V De-emphasized differential output voltage TX-DE-RATIO V DC Common mode voltage ...

Page 16

... IDT 89HPES12NT3 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. ...

Page 17

... IDT 89HPES12NT3 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES12NT3 The following table lists the pin numbers and signal names for the PES12NT3 device. Pin Function Alt Pin A1 V E10 E11 SS A3 PEARP03 E12 A4 V CORE E13 DD A5 ...

Page 18

... IDT 89HPES12NT3 Data Sheet Pin Function Alt Pin B17 V CORE G8 DD B18 V CORE PEBRP00 G10 C2 PEBRN00 G11 C3 V G12 CORE G13 G14 G15 G16 G17 G18 SS C10 C11 C12 ...

Page 19

... IDT 89HPES12NT3 Data Sheet Pin Function Alt Pin D18 V CORE PEBTN00 J10 E2 PEBTP00 J11 E3 V CORE J12 J13 CORE J14 J15 J16 J17 J18 SS Alternate Signal Functions Function Alt Pin V CORE N18 PECTP01 ...

Page 20

... IDT 89HPES12NT3 Data Sheet Power Pins V Core V Core A10 F10 A12 F18 A14 G12 A15 B17 H10 B18 H12 C4 H18 C13 J6 C16 J9 D1 J10 D4 J13 D14 J15 D18 K18 E14 Core ...

Page 21

... IDT 89HPES12NT3 Data Sheet Ground Pins A17 A18 B10 B12 B14 B15 C11 D11 D13 D15 D16 G16 D17 H11 E11 H13 E13 H17 E16 ...

Page 22

... IDT 89HPES12NT3 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE PEALREV PEARN00 PEARN01 PEARN02 PEARN03 PEARP00 PEARP01 PEARP02 PEARP03 PEATN00 ...

Page 23

... IDT 89HPES12NT3 Data Sheet Signal Name PEATN03 PEATP00 PEATP01 PEATP02 PEATP03 PEBLREV PEBRN00 PEBRN01 PEBRN02 PEBRN03 PEBRP00 PEBRP01 PEBRP02 PEBRP03 PEBTN00 PEBTN01 PEBTN02 PEBTN03 PEBTP00 PEBTP01 PEBTP02 PEBTP03 PECLREV PECRN00 PECRN01 PECRN02 PECRN03 PECRP00 PECRP01 PECRP02 PECRP03 PECTN00 PECTN01 PECTN02 PECTN03 ...

Page 24

... IDT 89HPES12NT3 Data Sheet Signal Name PECTP01 PECTP02 PECTP03 PENTBRSTN PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location O N18 O G18 O E17 I V12 ...

Page 25

... IDT 89HPES12NT3 Data Sheet PES12NT3 Pinout — Top View Core (Power I/O (Power (Power (Power APE (Power Signals ...

Page 26

... IDT 89HPES12NT3 Data Sheet PES12NT3 Package Drawing — 324-Pin BC324/BCG324 April 11, 2007 ...

Page 27

... IDT 89HPES12NT3 Data Sheet PES12NT3 Package Drawing — Page Two April 11, 2007 ...

Page 28

... IDT 89HPES12NT3 Data Sheet Revision History March 15, 2007: Initial publication of Preliminary data sheet. April 11, 2007: In Table 2, revised description of MSMBCLK April 11, 2007 ...

Page 29

... IDT 89HPES12NT3 Data Sheet Ordering Information A AAA NN Product Operating Device Family Voltage Family Valid Combinations 89HPES12NT3ZABC 324-pin BC324 package, Commercial Temperature 89HPES12NT3ZABCG 324-pin Green BC324 package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 NNAAN AA AA Package ...

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