89hpes12n3 Integrated Device Technology, 89hpes12n3 Datasheet
89hpes12n3
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89hpes12n3 Summary of contents
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... Device Overview The 89HPES12N3 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES12N3 is a 12-lane, 3-port periph- eral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides connectivity and switching functions between a PCIe® ...
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... IDT 89HPES12N3 Data Sheet ◆ Two SMBus Interfaces – Slave interface provides full access to all software-visible registers by an external SMBus master – Master interface provides connection for an optional serial EEPROM used for initialization – Master interface is also used by an external Hot-Plug I/O expander – ...
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... IDT 89HPES12N3 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12N3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...
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... IDT 89HPES12N3 Data Sheet Signal SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] Type Name/Description I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus ...
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... IDT 89HPES12N3 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT TSTRSVD SWMODE[3:0] Signal JTAG_TCK JTAG_TDI Type Name/Description I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports ...
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... IDT 89HPES12N3 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated ...
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... IDT 89HPES12N3 Data Sheet Pin Characteristics Note: Some input pads of the PES12N3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...
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... IDT 89HPES12N3 Data Sheet Function System Pins JTAG Pin Name Type Buffer CCLKDS I LVTTL CCLKUS I MSMBSMODE I PERSTN I RSTHALT I TSTRSVD I SWMODE[3:0] I JTAG_TCK I LVTTL JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_TRST_N I Table 7 Pin Characteristics (Part I/O Internal Notes Type Resistor Input pull-up pull-up pull-down ...
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... IDT 89HPES12N3 Data Sheet Logic Diagram — PES12N3 Reference Clock PCI Express Switch SerDes Input Port A PCI Express Switch SerDes Input Port B PCI Express Switch SerDes Input Port C Master SMBus Interface SSMBADDR[5,3:1] Slave SMBus Interface System Pins 2 PEREFCLKP 2 PEREFCLKN REFCLKM PEALREV ...
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... IDT 89HPES12N3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing ...
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... IDT 89HPES12N3 Data Sheet Parameter T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ENTER TIME T Lane to lane input skew RX-SKEW 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a ...
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... IDT 89HPES12N3 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power PCI Express Serial Data Transmit ...
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... IDT 89HPES12N3 Data Sheet Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES12N3, the power-up sequence must be as follows I/O — 3. Core, V PE, V APE — 1. — ...
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... IDT 89HPES12N3 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V Differential peak-to-peak output voltage TX-DIFFp-p V De-emphasized differential output voltage TX-DE-RATIO V DC Common mode voltage ...
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... IDT 89HPES12N3 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. ...
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... IDT 89HPES12N3 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES12N3 The following table lists the pin numbers and signal names for the PES12N3 device. Pin Function Alt Pin A1 V E10 E11 SS A3 PEARP03 E12 A4 V CORE E13 DD A5 ...
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... IDT 89HPES12N3 Data Sheet Pin Function Alt Pin B17 V CORE G8 DD B18 V CORE PEBRP00 G10 C2 PEBRN00 G11 C3 V G12 CORE G13 G14 G15 G16 G17 G18 SS C10 C11 C12 ...
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... IDT 89HPES12N3 Data Sheet Pin Function Alt Pin D18 V CORE PEBTN00 J10 E2 PEBTP00 J11 E3 V CORE J12 J13 CORE J14 J15 J16 J17 J18 SS Alternate Signal Functions Function Alt Pin V CORE N18 PECTP01 ...
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... IDT 89HPES12N3 Data Sheet Power Pins V Core V Core A10 F10 A12 F18 A14 G12 A15 B17 H10 B18 H12 C4 H18 C13 J6 C16 J9 D1 J10 D4 J13 D14 J15 D18 K18 E14 Core ...
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... IDT 89HPES12N3 Data Sheet Ground Pins A17 A18 B10 B12 B14 B15 C11 D11 D13 D15 G11 D16 G13 D17 G16 E11 H11 E13 H13 E16 H17 F2 J3 ...
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... IDT 89HPES12N3 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE PEALREV PEARN00 PEARN01 PEARN02 PEARN03 PEARP00 PEARP01 PEARP02 PEARP03 PEATN00 ...
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... IDT 89HPES12N3 Data Sheet Signal Name PEATN03 PEATP00 PEATP01 PEATP02 PEATP03 PEBLREV PEBRN00 PEBRN01 PEBRN02 PEBRN03 PEBRP00 PEBRP01 PEBRP02 PEBRP03 PEBTN00 PEBTN01 PEBTN02 PEBTN03 PEBTP00 PEBTP01 PEBTP02 PEBTP03 PECLREV PECRN00 PECRN01 PECRN02 PECRN03 PECRP00 PECRP01 PECRP02 PECRP03 PECTN00 PECTN01 PECTN02 PECTN03 ...
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... IDT 89HPES12N3 Data Sheet Signal Name PECTP01 PECTP02 PECTP03 PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 TSTRSVD SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location O N18 O G18 O E17 I V4 ...
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... IDT 89HPES12N3 Data Sheet PES12N3 Pinout — Top View Core (Power I/O (Power (Power (Power APE (Power Signals ...
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... IDT 89HPES12N3 Data Sheet PES12N3 Package Drawing — 324-Pin BC324/BCG324 July 18, 2006 ...
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... IDT 89HPES12N3 Data Sheet PES12N3 Package Drawing — Page Two July 18, 2006 ...
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... IDT 89HPES12N3 Data Sheet Revision History July 18, 2006: Publication of YC data sheet July 18, 2006 ...
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... IDT 89HPES12N3 Data Sheet Ordering Information A AAA NN Product Operating Device Family Voltage Family Valid Combinations 89HPES12N3YCBC 324-pin BC324 package, Commercial Temperature 89HPES12N3YCBCG 324-pin Green BC324 package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 NNAN AA AA Package ...