at86rf211 ATMEL Corporation, at86rf211 Datasheet - Page 31

• Manufacturer Part Number: at86rf211
• Description: Fsk Transceiver For Ism Radio Applications
• Manufacturer: ATMEL Corporation

1942C–WIRE–06/02
•
The tolerance for the extraction of DATA rate must be nearly 2% of the RATE. The toler-
ance represents the step for the calculation of the rate.
If the tolerance is too high, rate value is reached earlier but the rate value could be
unstable (step too big).
If the tolerance is too low, it could be difficult to catch up the DATA and the clock recov-
ery could get lost.
Some tolerance values given for example, with tolerance = 2% x DATARATE:
•
The PLL lock function uses UP and DOWN signals from the internal phase detector.
These signals are analyzed synchronously with a clock frequency, depending of LDCK
bit programming (10 MHz or 20 MHz sampling).
LDCK is set to ‘1’ to double the clock frequency of the function PLL lock detect, to
increase the precision of the function.
N0LD2 triggers the unlock condition of the PLL.
N0LD2 = number of consecutive edges of the sampling clock with UP and DOWN active
before considering PLL unlocked.
This value must not be set to 0 or 1. The recommended value is default value, i.e. 2.
N1LD2 triggers the lock condition of the PLL.
N1LD2 = number of cycle at the PLL reference frequency, without any unlock condition
before considering PLL locked.
This value must not be set to 0.
It is recommended to use default values indicated in the table.
DATARATE[13:0]
(1067)
(2135)
(4269)
(10246)
DATATOL[7:0]
(3)
(4)
(vv)
(20)
(21)
(43)
(85)
(205)
Datatol Programming
PLL Lock Detect
10
10
10
10
10
10
10
10
10
10
10
10
Rate
9.6 kbps
4.8 kbps
2.4 kbps
1 kbps
Rate
64 kbps
50 kbps
……
10 kbps
9.6 kbps
4.8 kbps
2.4 kbps
1 kbps
Period
1 bit ~ 1067 x T
1 bit ~ 2135 x T
1 bit ~ 4269 x T
1 bit ~ 10246 x T
Period
1 bit ~ 3 x T
1 bit ~ 4 x T
1 bit ~ vv x T
1 bit ~ 20 x T
1 bit ~ 21 x T
1 bit ~ 43 x T
1 bit ~ 85 x T
1 bit ~ 205 x T
AT86RF211
31