at86rf401 ATMEL Corporation, at86rf401 Datasheet
at86rf401
Related parts for at86rf401
at86rf401 Summary of contents
Page 1
... Wireless PC Peripherals (Keyboard, Mouse) • Telemetry (Tire Pressure, Utility Meter, Asset Tracking) Description The Atmel AT86RF401 Smart RF Microtransmitter is a highly integrated, low-cost RF transmitter, combined with an AVR RISC microcontroller. It requires only a crystal, a single LiMnO coin cell (CR2032 or similar), three capacitors, an inductor and a tuned- ...
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... The RF signal output is placed dif- ferentially on a tuned-loop antenna, which may be realized as a counterspread copper trace on a PCB. The AT86RF401 is fabricated in Atmel’s 0.6 µm Mixed Signal CMOS + EEPROM pro- cess, enabling true system-level integration (SLI). Figure 2. 20-lead TSSOP ...
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... S2 Y1 Value Value (315 MHz) (433.92 MHz) Antenna Dependent Not req’d Not req’d Not req’d Not req’ Not req’d Not req’d 13.125 MHz 18.08 MHz AT86RF401 20 ANT AVDD 17 DVDD 16 AGND IO5 13 IO4 ...
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... V VCO V DD LOOPFIL VCO VDD AT86RF401 4 Description 20 Differential Antenna Output External VCO Loop-filter Connection the VCO control voltage. VCO External VCO Inductor Connection the VCO control voltage. VCO 4 ...
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... SPI Clock/Input/Output 2: General-purpose I/O and button 9 input. In SPI mode, this pin serves as SCK (SPI Clock Input). To AVR 40 pF Crystal/Clock Input: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. This pin may be driven externally for test purposes AT86RF401 is above the brown ...
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... Enable Data Enable IO4 13 Data Enable Data Enable IO5 14 Data Enable DGND 15 AGND 16 DVDD 17 AT86RF401 Crystal Output: Output from the inverting oscillator amplifier Input/Output 3: General-purpose I/O and button input To AVR Input/Output 4: General-purpose I/O and button input ...
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... Table 2. Pin Descriptions – 20-lead TSSOP (Continued) AVDD 18 N ANT 20 1424F–RKE–12/03 Analog Voltage Supply No Connect – Float Pin 20 Differential Antenna Output 10 mA AT86RF401 7 ...
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... Low-level Output Voltage OL Microcontroller/System t Time from Button Wake- Outputs Active TX f AVR Clock Frequency AVR EE EEPROM Retention LIFE EE EEPROM Write/Erase Endurance CYCLES AT86RF401 8 *NOTICE 10V 40°C to +85°C 55°C to +125°C 0 +0. 16 25°C unless otherwise specified. XTAL A Conditions ...
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... VCO control voltage. An internal window comparator monitors the magnitude of the tun- ing voltage and is used by the AVR core to determine the optimal tuning configuration. The lock detection block provides an indication of the state of the phase lock loop (PLL). Lock condition is determined by counting the number of cycle slips in a given time AT86RF401 Min Typ Max Unit – ...
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... Brown-out Protection/Low Battery Detection Brown-out Protection Low Battery Detection AT86RF401 10 period. A number of registers are available to adjust the performance of the lock detec- tor. These include lock delay and unlock delay timers as well as a cycle slip counter. The device uses a 1.2V (nominal) bandgap reference generator to provide consistent performance over a wide range of input supply voltages ...
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... Using polling instead of interrupts may facilitate higher bit rates. Additionally, this timer may be used to time pulses arriving at the I/O3 pin. This enables the AT86RF401 to be used to decode the signal detected by an external receiver chip. For additional information on how to implement the bit timer, see AT86RF401 Bit Timer Application Note, available at www ...
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... The system clock is determined by Bits[7:5] of the AVR_CONFIG register. The AT86RF401 Reset and Interrupt vectors are defined in Table 5. The I-bit in the sta- tus register must be set to enable the interrupts. ...
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... Same as mode 2, but Verify is also disabled Note: The lock bits can only be erased with the Chip Erase operation. The AT86RF401 offers 2 Kbytes (1K x 16) of in-system reprogrammable Flash program memory and 128 bytes of EEPROM data memory. This memory can be programmed serially via the SPI interface. ...
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... Signature Bytes AT86RF401 14 Refer to Figure 4 (page 15), Figure 5 (page 16) and Figure 6 (page 17). To program and verify the AT86RF401 in the serial programming mode, the following sequence is recommended. Power-up Sequence: 1. Apply power between VDD and GND while RESETB and SCK are set to “0” crystal is not connected across pins XTAL and XTALB, apply a clock signal to the XTAL pin ...
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... Data EEPROM Access from the AVR Table 7. AT86RF401 Serial Programming Instruction Set Instruction Byte 1 Programming 1010 1100 Enable Chip Erase 1010 1100 Read Program 0010 H000 Memory Write Program 0100 H000 Memory Read 1010 0000 EEPROM Memory Write 1100 0000 EEPROM Memory ...
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... The ALU supports arithmetic and logic operations between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 6 shows the AT86RF401 AVR architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowest data space addresses ($00– ...
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... The 7-bit stack pointer SP is read/write accessible in the I/O space. The 128-byte data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. AT86RF401 Data Bus 8-bit Status and Control Bit Timer ...
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... AT86RF401 18 A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The inter- rupts have priority in accordance with their interrupt vector position; the lower the interrupt vector address, the higher the priority ...
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... Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X, Y and Z registers can be set to index any register in the file. AT86RF401 0 Addr. R0 $00 ...
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... The multiplier is not present in this ver- sion of the core. Therefore, the MUL instruction is not supported. The AT86RF401 contains 2 Kbytes of on-chip Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized 16. ...
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... X, Y and Z are decremented and incremented. The 32 general-purpose working registers, 64 I/O registers and the 128 bytes of internal data SRAM in the AT86RF401 are all accessible through all these addressing modes. The AT86RF401 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM, Register File and I/O Memory) ...
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... Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct AT86RF401 22 Figure 11. Direct Single Register Addressing The operand is contained in register d (Rd). Figure 12. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 13. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. “ ...
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... OP n Operand address is the result of the register contents added to the address con- tained in 6 bits of the instruction word. Figure 16. Data Indirect Addressing REGISTER Operand address is the contents of the register. AT86RF401 Data Space $ Rr/Rd 0 $DF Data Space ...
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... Data Indirect with Pre-decrement Data Indirect with Post-increment Constant Addressing Using the LPM Instruction AT86RF401 24 Figure 17. Data Indirect Addressing with Pre-decrement REGISTER The register is decremented before the operation. Operand address is the decremented contents of the register. ...
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... Figure 20. Indirect Program Memory Addressing Program execution continues at address contained by the Z register (i.e., the PC is loaded with the contents of the Z register). Figure 21. Relative Program Memory Addressing Program execution continues at address The relative address k is from 2048 to 2047. AT86RF401 $3FF 1 $3FF 25 ...
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... Execution Timing AT86RF401 26 The AT86RF401 contains 128 bytes of data EEPROM memory organized as a sep- arate data space in which single bytes can be read and written. The access between the EEPROM and the CPU is described in the Memory Programming section (page 13). This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ø ...
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... SBI instructions will operate on all bits in the I/O register, writing a “1” back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. The I/O and peripherals control registers are explained in the following sections. AT86RF401 T2 T3 Address ...
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... I/O Memory The I/O space definition of the AT86RF401 is shown in Table 8 below. Table 8. AT86RF401 I/O Space Definitions Address Hex $3F $3E $3D $35 $34 $33 $32 $31 $30 $22 $21 $20 $1E $1D $1C $17 $16 $14 $12 $10 Note: Reserved and unused locations are not shown in the table. AT86RF401 28 Name Function SREG Status Register ...
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... Initial Value 0 1424F–RKE–12/03 The AT86RF401 I/Os and peripherals are placed in the I/O space. The various I/O loca- tions are accessed by the IN and OUT instructions transferring data between the 32 general-purpose working registers and the I/O space. I/O registers within the address range $00–$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instruc- tions ...
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... Bit 7 $12 – Read/Write R/W Initial Value 0 Power Attenuation Control Register – PWR_ATTEN Bit 7 $14 – Read/Write R/W Initial Value 0 AT86RF401 – TXE TXK R/W R/W R • Bit[7:6] Reserved. • Bit[5]: TXE, Transmitter Enable This bit, when set, turns on the phase locked loop (PLL) RF frequency synthesizer but should not be used to modulate the RF carrier or excessive spurious noise may result. • ...
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... VCO. A switched array of tuning capacitors has been added internally to the device in order to “fine tune” the VCO. This capacitance is switched across pins 3 and 4 (L1 and L2) of the device. The capacitor array is set by VCOTUNE[4:0] and is comprised of the following switched capacitance levels: AT86RF401 Output Attenuation ...
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... AT86RF401 32 Table 12. VCO Tuning Capacitor Definition VCOTUNE[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Capacitance (pF ...
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... Forces the lockdetect signal to “1” at the output of the lock detect circuitry. This may be useful if the lock detect signal is not going high for some reason, and a power amp inter- lock has been implemented, and the user wishes to enable the power amp output stage. AT86RF401 3 2 ...
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... AT86RF401 34 • Bit[5:3]: ULC[2:0] The unlock count (ULC) bits count a certain number of reference clocks, after which the unlock detect circuit looks for a number of cycle slips determined by CS[1:0] before making the loc detect signal go low. The ULC bits essentially control the blackout period of the unlock detect circuit ...
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... Bit[0]: EEPROM Read Bit To read the EEPROM use the following procedure: 1. Write the address to the DEEAR. 2. Set the read bit. 3. Read the data register. The read bit will reset itself another read needs to be done, repeat steps 1–3 again. AT86RF401 BSY EEU ...
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... ED7 Read/Write R/W Initial Value 0 0 Data EEPROM Address Register – DEEAR Bit 7 $1E – Read/Write R/W Initial Value 0 0 AT86RF401 ED6 ED5 ED4 R/W R/W R • Bits[7:0] This register contains the byte to be written to EEPROM read operation has been done, this register contains that last byte read from the data EEPROM ...
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... Flag0 interrupt vector is located 04. Flag2 interrupt vector is located 02. Typically, a JMP instruction resides at these vector locations to pass control to an interrupt handler. For Flag0 only, slightly faster execution can be achieved if the JMP instruction is eliminated, and the interrupt service routine is located beginning 04. AT86RF401 ...
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... R R Initial Value 0 0 AT86RF401 38 • Bit[2]: Flag2 In transmit mode, this flag indicates the Transmit Done condition that occurs when the buffer is empty and the counter has counted down to “0”. In receive mode, this flag indi- cates that an edge has occurred, and the AVR should process the count value in the BTCR and BTCNT registers ...
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... Bit[7] Reserved. • Bit[6] If set to “1”, additional hysteresis is added to the battery low and brown-out logic. See BL_CONFIG register description and Table 21 on page 43 for more details. AT86RF401 WDP0 Number of System Clock Cycles 0 2,048 cycles 1 4,096 cycles 0 8,192 cycles ...
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... Read/Write R/W Initial Value 0 AT86RF401 40 • Bits[5:0] If set to “1”, the corresponding bit (pin) IO[5:0] is configured as an output. Data may then be written to that output by writing to the IO_DATA register. If set to “0”, the correspond- ing bit (pin) may be either a button input (refer to the Button Detect Register, $34) used to wake the part normal digital input ...
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... Bit[0]: Button Boot Mode (BBM) If the BBM bit is set and the part is brought out of sleep mode by a button input activa- tion, the part will enter the button reset state. In this state, the part will reboot and begin AT86RF401 AVR System Clock XTALB/16 ...
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... Read/Write R Initial Value 0 Battery Low Configuration Register – BL_CONFIG Bit 7 $35 BL Read/Write R Initial Value 0 AT86RF401 42 code execution at the reset location. This bit is reset at POR and when exiting the button reset state. All other registers remain unchanged – BD5 BD4 R R/W R/W 0 ...
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... Falling DD 3.887 V REF VDD = ---------------------------------------------------------- - 0.887 -------------- - 1 + BL[5: REF BL[5:0] 71 3.887 ------------ - = V DD 1424F–RKE–12/03 is approximately 0.7 volts) REF BOHYST = 1 (large hysteresis) 4.05 V REF VDD = ---------------------------------------------------------- - 0.887 -------------- - ------------ - BL[5: 4.05 1 – AT86RF401 V Rising DD BOHYST = 0 (small hysteresis) 4.22 VDD = ---------------------------------------------------------- - 0.887 -------------- - 1 + BL[5:0] 63 REF – 1 BL[5: 4. REF BL[5:0] V REF ------------ - – ...
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... Bit 7 $3F I Read/Write R/W Initial Value 0 AT86RF401 44 The Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). Caution: As the data memory has 224 locations, only 8 bits are used and the SPH register must be programmed 00 – – ...
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... Rdh:Rdl Rdh:Rdl $ AT86RF401 Flags Z,C,N,V,H Z,C,N,V,H Rdh:Rdl + K Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Rdh:Rdl - K Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Rr Z,N,V Rd Z,C,N,V Rd Z,C,N,V,H Z,N,V Z,N,V Z,N,V 1 Z,N,V Z,N,V #Clocks ...
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... Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag Set AT86RF401 46 Operation $ ...
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... Rr (Y) Rr ( (Z) Rr ( (Z) Rd (Z) Rd (Z AT86RF401 Flags #Clocks None 1/2 None 1/2 None 1/2 None 1 None None 1 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None ...
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... Set Two’s Complement Overflow CLV Clear Two’s Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half Carry Flag in SREG CLH Clear Half Carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset AT86RF401 48 Operation P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) ...
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... Ordering Information RF Output Ordering Code 315 MHz AT86RF401U 434 MHz AT86RF401E 264 to 456 MHz AT86RF401X 1424F–RKE–12/03 Package Application 20T North American 20T European 20T All Applications AT86RF401 Temperature Operating Range ...
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... Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and determined at Datum Plane H. 2325 Orchard Parkway San Jose, CA 95131 R AT86RF401 50 All devices are packaged on tape in reel; standard reel quantity is 2,500 pieces TITLE 20A2, 20-lead (4 ...
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... Added note regarding maximum output power in Power Attenuation Control Register description section (page 30). • Added text to “Button Reset” paragraph in the Reset Sources section (page 12). • Added text to Bit Timer section (page 11). • Added text to Bit Timer Control Register section (page 37). AT86RF401 51 ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibil ity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wit h out notice, and does not make any commitment to update the information contained herein ...